/spl Sigma//spl Delta/ ADC with finite impulse response feedback DAC

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332601

Bas M. Putter

引用次数: 65

Abstract

A continuous-time 1 b /spl Sigma//spl Delta/ ADC with a finite impulse response DAC in the feedback path is presented. The FIRDAC reduces the susceptibility to clock jitter by 18 dB while maintaining linearity. S/N ratio is 77 dB in a 1 MHz bandwidth, and IM2 and IM3 are 77 dB and 82 dB, respectively. The 0.18 /spl mu/m CMOS chip consumes 6.0 mW.

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/spl Sigma//spl Delta/ ADC，具有有限脉冲响应反馈DAC

提出了一种具有有限脉冲响应的连续时间1 b /spl σ //spl δ / ADC。FIRDAC在保持线性度的同时，将时钟抖动的敏感性降低了18 dB。1mhz带宽下信噪比为77 dB, IM2和IM3分别为77 dB和82 dB。0.18 /spl mu/m的CMOS芯片消耗6.0 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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