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2020 International SoC Design Conference (ISOCC)最新文献

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A Design of Charge Pump for Low Noise Phase-Locked Loops using Clock Quadrature 基于时钟正交的低噪声锁相环电荷泵设计
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333003
M. Kim, Kangyoon Lee
{"title":"A Design of Charge Pump for Low Noise Phase-Locked Loops using Clock Quadrature","authors":"M. Kim, Kangyoon Lee","doi":"10.1109/ISOCC50952.2020.9333003","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333003","url":null,"abstract":"This paper proposes A Design of charge pump for fast rising and falling time and adequate for Sigma Delta Modulation (SDM). Low Noise Phase-Locked Loop (PLL) architecture using reference clock quadrature is shown. The degree of noise performance improvement that can be obtained using clock quadrature is expressed in an expression. To fulfill the speed of the quadrupled reference clock, fully differential charge pump (CP) architecture is used. Also, Implemented the design of a unity gain buffer in charge pump for the optimized operation for Sigma Delta Modulation (SDM) which is also adequate for wide bandwidth PLL because of the high bandwidth and the ability to handle high load current. The proposed structure is implemented using CMOS 40nm process and uses 1.1V supply power.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Chaotic True Random Number Generator for Secure Communication Applications 用于安全通信应用的混沌真随机数发生器
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333113
Alaaddin Al-Shidaifat, C. Jayawickrama, Yechan Jung, S. Lee, Hanjung Song, N. Kahraman
{"title":"Chaotic True Random Number Generator for Secure Communication Applications","authors":"Alaaddin Al-Shidaifat, C. Jayawickrama, Yechan Jung, S. Lee, Hanjung Song, N. Kahraman","doi":"10.1109/ISOCC50952.2020.9333113","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333113","url":null,"abstract":"This work is proposed chaotic true random number generator (TRNG) based on chaotic PWM sequence generator. The chaos CMOS circuit presents here is the chaotic sequence generator. The main components of the chaotic PWM circuit is chaotic sequence generator for chaotic triangular waveforms. The chaotic TRNG was designed by using 0.18μm CMOS process. The full system is prose to be a implementation of IoT secure data communication system using chaotic security.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125473178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes 非二进制准循环LDPC码的高效校验节点单元结构
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333048
Thang Xuan Pham, Hanho Lee
{"title":"Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes","authors":"Thang Xuan Pham, Hanho Lee","doi":"10.1109/ISOCC50952.2020.9333048","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333048","url":null,"abstract":"In this paper, an efficient check node unit (CNU) architecture with a high output message compression ratio is introduced in order to reduce the hardware resources requirement for non-binary low-density parity-check (NB-LDPC) decoder. The new compression technique is proposed by observing the intrinsic message, where $boldsymbol{L}$ intrinsic messages are able to reduce to $S(S < L)$ group representative values. The hardware implementation results show that the proposed design is able to achieve the lowest hardware consumption and a better clock frequency compared with its predecessors.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123389408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scheduling of Rigid Tasks on Heterogeneous Multicores 异构多核下刚性任务调度
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333098
Takava Watanabe, Hiroki Nishikawa, H. Tomiyama
{"title":"Scheduling of Rigid Tasks on Heterogeneous Multicores","authors":"Takava Watanabe, Hiroki Nishikawa, H. Tomiyama","doi":"10.1109/ISOCC50952.2020.9333098","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333098","url":null,"abstract":"This paper presents scheduling of rigid tasks on heterogeneous multicore architecture. The proposed technique, based on integer linear programming, determines mapping of tasks and the type of cores to execute each task. The goal is minimization of the overall schedule length. Experimental results show the effectiveness of our scheduling technique.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116592189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Operation and Stability Analysis of Temperature-Insensitive MOS Reference Current Source with Self-Bias Circuit 带自偏置电路的温度不敏感MOS基准电流源的工作及稳定性分析
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332805
Souma Yamamoto, Kuswan Isam Ebisawa, Yudai Abe, Takashi Ida, Y. Shibasaki, N. Tsukiji, A. Kuwana, Haruo Kobayashi, Akira Suzuki, Yukichi Todoroki, Toshihiko Kakinoki, Nobuto Ono, Kazuhiro Miura
{"title":"Operation and Stability Analysis of Temperature-Insensitive MOS Reference Current Source with Self-Bias Circuit","authors":"Souma Yamamoto, Kuswan Isam Ebisawa, Yudai Abe, Takashi Ida, Y. Shibasaki, N. Tsukiji, A. Kuwana, Haruo Kobayashi, Akira Suzuki, Yukichi Todoroki, Toshihiko Kakinoki, Nobuto Ono, Kazuhiro Miura","doi":"10.1109/ISOCC50952.2020.9332805","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332805","url":null,"abstract":"This paper analyzes our proposed temperature-insensitive MOS reference current source. It uses a self-bias circuit with feedback configuration, which may cause the circuit instability. Its stability condition has been investigated based on feedback theory as well as simulation.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123754001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Ultra-Low-Power Tunable Bump Circuit using Source-Degenerated Differential Transconductor 一种超低功耗可调凹凸电路
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332988
Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
{"title":"An Ultra-Low-Power Tunable Bump Circuit using Source-Degenerated Differential Transconductor","authors":"Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim","doi":"10.1109/ISOCC50952.2020.9332988","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332988","url":null,"abstract":"In this paper, we proposed a nano-power tunable bump circuit. It incorporates a novel source-degenerated transconductor using pseudo-resistor as source resistor to control the width of the bump. The presented circuit is simulated in Cadence using 180nm CMOS process under 1.8V power supply. The results show that the transconductance is tuned with pseudo-resistor and the bump circuit can operate with wide voltage range from 0.3V to 1.8V. Also, this circuit is compact and only dissipates 16.7nW power which makes it perfect for large-scale machine learning applications such as classifier and support vector machine.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115179586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of Synchronization Phenomena in Coupled Two-degrees-of-Freedom Chaotic Circuits 耦合二自由度混沌电路中同步现象的研究
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333050
Naoto Yonemoto, Katsuya Nakabai, Y. Uwate, Y. Nishio
{"title":"Investigation of Synchronization Phenomena in Coupled Two-degrees-of-Freedom Chaotic Circuits","authors":"Naoto Yonemoto, Katsuya Nakabai, Y. Uwate, Y. Nishio","doi":"10.1109/ISOCC50952.2020.9333050","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333050","url":null,"abstract":"This paper considers synchronization phenomena in coupled two-degrees-of-freedom chaotic circuits by a resister. It is considered that studying various cases of synchronization phenomena when using chaotic circuits showing asynchronous simultaneous oscillation will be useful in clarifying non-linear phenomena that exist around us. By means of the circuit experiments and computer simulations, chaotic attractors and Lissajous figures are shown. From the results, synchronization phenomenon was confirmed between the circuits farthest from the connection part.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123066664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pedestrian Detection in Infrared Thermal Images Based on Raised Cosine Distribution 基于提升余弦分布的红外热图像行人检测
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332804
Manikanta Prahlad Manda, Chan Su Park, ByeongCheol Oh, Dai-Kyung Hyun, Hi-Seok Kim
{"title":"Pedestrian Detection in Infrared Thermal Images Based on Raised Cosine Distribution","authors":"Manikanta Prahlad Manda, Chan Su Park, ByeongCheol Oh, Dai-Kyung Hyun, Hi-Seok Kim","doi":"10.1109/ISOCC50952.2020.9332804","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332804","url":null,"abstract":"We propose a simple and fast image thresholding approach for detecting pedestrians in an infrared thermal image. The approach uses the raised cosine distribution function as an analogous function to the one-dimensional histogram of the infrared thermal image. Experiments are conducted on the infrared thermal images gathered from the standard infrared image datasets to describe the performance of the proposed method. The performance is evaluated by comparing the results with state-of-art methods.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115135367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FPGA implementation of sequence-to-sequence predicting spiking neural networks 序列对序列预测尖峰神经网络的FPGA实现
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332910
Changmin Ye, V. Kornijcuk, Jeeson Kim, D. Jeong
{"title":"FPGA implementation of sequence-to-sequence predicting spiking neural networks","authors":"Changmin Ye, V. Kornijcuk, Jeeson Kim, D. Jeong","doi":"10.1109/ISOCC50952.2020.9332910","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332910","url":null,"abstract":"We propose a hardware-efficient method to implement sequence-predicting spiking neural networks (SPSNN) on a field-programmable gate array board. The SPSNN is capable of sequence-to-sequence prediction (associative recall) when fully trained using the learning by backpropagating action potential (LbAP) algorithm. The key to the hardware-efficiency lies in the rule-based event (routing) method in place of conventional lookup-table-based methods which are memory-hungry methods, particularly, when both forward and inverse lookups should be considered.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"278 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133990523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-band PLL for RF wireless charger at 2.4 GHz and 5.8 GHz 用于2.4 GHz和5.8 GHz射频无线充电器的多频段锁相环
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333120
Joonhong Park, David Kim, Ree Jin Joe, JongWan Jo, Younggun Pu, Kangyoon Lee
{"title":"Multi-band PLL for RF wireless charger at 2.4 GHz and 5.8 GHz","authors":"Joonhong Park, David Kim, Ree Jin Joe, JongWan Jo, Younggun Pu, Kangyoon Lee","doi":"10.1109/ISOCC50952.2020.9333120","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333120","url":null,"abstract":"This paper presents an integer-N Phase Locked Loop (PLL) for the use in RF wireless charger systems. The presented design supports 4.3 GHz to 6.3 GHz bands using a push-pull Class-C Voltage Controlled Oscillator (VCO) structure. The 2.4 GHz frequency is generated by dividing 4.8 GHz by 2 times to reduce current consumption. Reference spur levels are lower than -45 dBc. The PLL consumes less than 36 mW from a 1.8 V power supply with a settling time less than 40 µs and the area is 1200 µm × 1100 µm in the TSMC 180 nm CMOS process.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115691006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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