{"title":"非二进制准循环LDPC码的高效校验节点单元结构","authors":"Thang Xuan Pham, Hanho Lee","doi":"10.1109/ISOCC50952.2020.9333048","DOIUrl":null,"url":null,"abstract":"In this paper, an efficient check node unit (CNU) architecture with a high output message compression ratio is introduced in order to reduce the hardware resources requirement for non-binary low-density parity-check (NB-LDPC) decoder. The new compression technique is proposed by observing the intrinsic message, where $\\boldsymbol{L}$ intrinsic messages are able to reduce to $S(S < L)$ group representative values. The hardware implementation results show that the proposed design is able to achieve the lowest hardware consumption and a better clock frequency compared with its predecessors.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes\",\"authors\":\"Thang Xuan Pham, Hanho Lee\",\"doi\":\"10.1109/ISOCC50952.2020.9333048\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, an efficient check node unit (CNU) architecture with a high output message compression ratio is introduced in order to reduce the hardware resources requirement for non-binary low-density parity-check (NB-LDPC) decoder. The new compression technique is proposed by observing the intrinsic message, where $\\\\boldsymbol{L}$ intrinsic messages are able to reduce to $S(S < L)$ group representative values. The hardware implementation results show that the proposed design is able to achieve the lowest hardware consumption and a better clock frequency compared with its predecessors.\",\"PeriodicalId\":270577,\"journal\":{\"name\":\"2020 International SoC Design Conference (ISOCC)\",\"volume\":\"212 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC50952.2020.9333048\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC50952.2020.9333048","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes
In this paper, an efficient check node unit (CNU) architecture with a high output message compression ratio is introduced in order to reduce the hardware resources requirement for non-binary low-density parity-check (NB-LDPC) decoder. The new compression technique is proposed by observing the intrinsic message, where $\boldsymbol{L}$ intrinsic messages are able to reduce to $S(S < L)$ group representative values. The hardware implementation results show that the proposed design is able to achieve the lowest hardware consumption and a better clock frequency compared with its predecessors.