Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes

Abstract

In this paper, an efficient check node unit (CNU) architecture with a high output message compression ratio is introduced in order to reduce the hardware resources requirement for non-binary low-density parity-check (NB-LDPC) decoder. The new compression technique is proposed by observing the intrinsic message, where $\boldsymbol{L}$ intrinsic messages are able to reduce to $S(S < L)$ group representative values. The hardware implementation results show that the proposed design is able to achieve the lowest hardware consumption and a better clock frequency compared with its predecessors.