A Design of Charge Pump for Low Noise Phase-Locked Loops using Clock Quadrature

Abstract

This paper proposes A Design of charge pump for fast rising and falling time and adequate for Sigma Delta Modulation (SDM). Low Noise Phase-Locked Loop (PLL) architecture using reference clock quadrature is shown. The degree of noise performance improvement that can be obtained using clock quadrature is expressed in an expression. To fulfill the speed of the quadrupled reference clock, fully differential charge pump (CP) architecture is used. Also, Implemented the design of a unity gain buffer in charge pump for the optimized operation for Sigma Delta Modulation (SDM) which is also adequate for wide bandwidth PLL because of the high bandwidth and the ability to handle high load current. The proposed structure is implemented using CMOS 40nm process and uses 1.1V supply power.