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DAC Design Automation Conference 2012最新文献

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Obstacle-avoiding free-assignment routing for flip-chip designs 倒装芯片设计的避障自由分配路由
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228558
Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen
{"title":"Obstacle-avoiding free-assignment routing for flip-chip designs","authors":"Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen","doi":"10.1145/2228360.2228558","DOIUrl":"https://doi.org/10.1145/2228360.2228558","url":null,"abstract":"The flip-chip packaging is introduced for modern IC designs with higher integration density and larger I/O counts. It is necessary to consider routing obstacles for modern flip-chip designs, where the obstacles could be regions blocked for signal integrity protection (especially for analog/mixed-signal modules), pre-routed or power/ground nets, and even for through-silicon vias for 3D IC designs. However, no existing published works consider obstacles. To remedy this insufficiency, this paper presents the first work to solve the free-assignment flip-chip routing problem considering obstacles. For the free-assignment routing problem, most existing works apply the network-flow formulation. Nevertheless, we observe that no existing network-flow model can exactly capture the routability of a local routing region (tile) in presence of obstacles. This paper presents the first work that can precisely model the routability of a tile, even with obstacles. Based on this new model, a two-stage approach of global routing followed by detailed routing is proposed. The global routing computes a routing topology by the minimum-cost maximum-flow algorithm, and the detailed routing determines the precise wire positions. Dynamic programming is applied to further merge tiles to reduce the problem size. Compared to a state-of-the-art flow model with obstacle handling extensions, experimental results show that our algorithm can achieve 100% routability for all circuits while the extensions of the previous work cannot complete routing for any benchmark circuit with obstacles.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127956809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Accuracy-configurable adder for approximate arithmetic designs 用于近似算术设计的精度可配置加法器
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228509
A. Kahng, Seokhyeong Kang
{"title":"Accuracy-configurable adder for approximate arithmetic designs","authors":"A. Kahng, Seokhyeong Kang","doi":"10.1145/2228360.2228509","DOIUrl":"https://doi.org/10.1145/2228360.2228509","url":null,"abstract":"Approximation can increase performance or reduce power consumption with a simplified or inaccurate circuit in application contexts where strict requirements are relaxed. For applications related to human senses, approximate arithmetic can be used to generate sufficient results rather than absolutely accurate results. Approximate design exploits a tradeoff of accuracy in computation versus performance and power. However, required accuracy varies according to applications, and 100% accurate results are still required in some situations. In this paper, we propose an accuracy-configurable approximate (ACA) adder for which the accuracy of results is configurable during runtime. Because of its configurability, the ACA adder can adaptively operate in both approximate (inaccurate) mode and accurate mode. The proposed adder can achieve significant throughput improvement and total power reduction over conventional adder designs. It can be used in accuracy-configurable applications, and improves the achievable tradeoff between performance/power and quality. The ACA adder achieves approximately 30% power reduction versus the conventional pipelined adder at the relaxed accuracy requirement.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129160366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 441
Invariance-based concurrent error detection for Advanced Encryption Standard 基于不变性的高级加密标准并发错误检测
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228463
Xiaofei Guo, R. Karri
{"title":"Invariance-based concurrent error detection for Advanced Encryption Standard","authors":"Xiaofei Guo, R. Karri","doi":"10.1145/2228360.2228463","DOIUrl":"https://doi.org/10.1145/2228360.2228463","url":null,"abstract":"Naturally occurring and maliciously injected faults reduce the reliability of Advanced Encryption Standard (AES) and may leak confidential information. We developed an invariance-based concurrent error detection (CED) scheme which is independent of the implementation of AES encryption/decryption. Additionally, we improve the security of our scheme with Randomized CED Round Insertion and adaptive checking. Experimental results show that the invariance-based CED scheme detects all single-bit, all singlebyte fault, and 99.99999997% of burst faults. The area and delay overheads of this scheme are compared with those of previously reported CED schemes on two Xilinx Virtex FPGAs. The hardware overhead is in the 13.2-27.3% range and the throughput is between 1.8-42.2Gbps depending on the AES architecture, FPGA family, and the detection latency. One can implement our scheme in many ways; designers can trade off performance, reliability, and security according to the available resources.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"63 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130615722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Recovery-based design for variation-tolerant SoCs 基于恢复的耐变soc设计
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228510
V. Kozhikkottu, S. Dey, A. Raghunathan
{"title":"Recovery-based design for variation-tolerant SoCs","authors":"V. Kozhikkottu, S. Dey, A. Raghunathan","doi":"10.1145/2228360.2228510","DOIUrl":"https://doi.org/10.1145/2228360.2228510","url":null,"abstract":"Parameter variations have emerged as a significant threat to continued CMOS scaling in the nanometer regime. Due to increasing performance penalties associated with worst-case design, recovery based design has emerged as a promising approach for dealing with the impact of variations. Previous work has applied recovery based design at the circuit and micro-architecture levels of abstraction. In this work, we address the problem of designing variation-tolerant SoCs using the recovery based design paradigm. We demonstrate that a monolithic implementation of recovery based design fails to scale for large SoCs. We propose the concept of recovery islands, wherein each island consists of one or more SoC components that can recover independent of the rest of the SoC, and demonstrate how our proposal can be easily realized via minor changes to a traditional SoC design flow. We study the tradeoffs involved in applying recovery based design at the system level. We demonstrate that it is critical to account for (i) the inherent diversity of the error-voltage profiles among various components in an SoC, and (ii) the impact of error recovery in a component on overall system performance. We then propose a systematic recovery-based SoC design methodology that partitions a given SoC into recovery islands and also computes the optimal operating points for each island, taking into account the various system level trade-offs involved. We evaluate our framework on three different SoC designs, an 802.11b MAC processor, an MPEG encoder and a Wireless Video Capture system and demonstrate an average of 32% energy savings over conventional designs.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130789950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Obtaining and reasoning about good enough software 获取和推理足够好的软件
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228526
M. Rinard
{"title":"Obtaining and reasoning about good enough software","authors":"M. Rinard","doi":"10.1145/2228360.2228526","DOIUrl":"https://doi.org/10.1145/2228360.2228526","url":null,"abstract":"Software systems often exhibit a surprising flexibility in the range of execution paths they can take to produce an acceptable result. This flexibility enables new techniques that augment systems with the ability to productively tolerate a wide range of errors. We show how to exploit this flexibility to obtain transformations that improve reliability and robustness or trade off accuracy in return for increased performance or decreased power consumption. We discuss how to use empirical, probabilistic, and statistical reasoning to understand why these techniques work.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"9 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116777417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Generalized SAT-sweeping for post-mapping optimization 映射后优化的广义sat扫描
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228507
Tobias Welp, Smita Krishnaswamy, A. Kuehlmann
{"title":"Generalized SAT-sweeping for post-mapping optimization","authors":"Tobias Welp, Smita Krishnaswamy, A. Kuehlmann","doi":"10.1145/2228360.2228507","DOIUrl":"https://doi.org/10.1145/2228360.2228507","url":null,"abstract":"Modern synthesis flows apply a series of technology independent optimization steps followed by mapping algorithms which bind the optimized network to a specific technology library. As the exact solution of the mapping problem is computationally intractable, algorithms used in practice use heuristic, typically tree-based approaches. The application of these algorithms results in mapped but suboptimal networks. In this work, we present a novel, efficient, and effective optimization algorithm for mapped networks which can be considered a generalization of SAT-sweeping. Our algorithm searches for alternative, more efficient implementations of each net in the network. Candidate support nets for reimplementation are selected using simulation signatures and verified using Boolean satisfiability. We report experimental results on the quality of our algorithm obtained from an implementation of the approach using the logic synthesis system ABC.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132457802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reversible statistical max/min operation: Concept and applications to timing 可逆统计最大/最小操作:概念及定时应用
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228554
D. Sinha, C. Visweswariah, Natesan Venkateswaran, Jinjun Xiong, V. Zolotov
{"title":"Reversible statistical max/min operation: Concept and applications to timing","authors":"D. Sinha, C. Visweswariah, Natesan Venkateswaran, Jinjun Xiong, V. Zolotov","doi":"10.1145/2228360.2228554","DOIUrl":"https://doi.org/10.1145/2228360.2228554","url":null,"abstract":"The increasing significance of variability in modern sub-micron manufacturing process has led to the development and use of statistical techniques for chip timing analysis and optimization. Statistical timing involves fundamental operations like statistical-add, sub, max and min to propagate timing information (modeled as random variables with known probability distributions) through a timing graph model of a chip design. Although incremental timing during optimization updates timing information of only certain parts of the timing-graph, lack of established reversible statistical max or min techniques forces more-than-required computations. This paper describes the concept of reversible statistical max and min for correlated Gaussian random variables, and suggests potential applications to statistical timing. A formal proof is presented to establish the uniqueness of reversible statistical max. Experimental results show run-time savings when using the presented technique in the context of chipslack computation during incremental timing optimization.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132561483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Material implication in CMOS: A new kind of logic CMOS中的材料蕴涵:一种新的逻辑
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228592
E. Roa, Wu-Hsin Chen, B. Jung
{"title":"Material implication in CMOS: A new kind of logic","authors":"E. Roa, Wu-Hsin Chen, B. Jung","doi":"10.1145/2228360.2228592","DOIUrl":"https://doi.org/10.1145/2228360.2228592","url":null,"abstract":"For more than seventy years, all the development in digital electronics have been founded on Shannon's work based on the fact that Boolean logic operators, OR, AND and NOT, can form a computationally complete logic framework. We propose a new paradigm in logic circuit design using material implication logic operators, different from the traditional logic gates in implementation and operation. In this paper we present early evidences, with experimental silicon results, showing that this new logic framework significantly improves performance, power and speed, over an equivalent conventional-logic framework in CMOS. This new computing paradigm would enable the continuance of increasing computing functionality and performance with decreasing cost in silicon technologies.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134272312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ComPLx: A competitive primal-dual Lagrange optimization for global placement 复杂:一个竞争的原对偶拉格朗日优化全局布局
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228496
Myung-Chul Kim, I. Markov
{"title":"ComPLx: A competitive primal-dual Lagrange optimization for global placement","authors":"Myung-Chul Kim, I. Markov","doi":"10.1145/2228360.2228496","DOIUrl":"https://doi.org/10.1145/2228360.2228496","url":null,"abstract":"We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the original non-convex problem into“more convex”sub-problems. It generalizes the recent SimPL, SimPLR and Ripple algorithms and extends them. Empirically, ComPLx outperforms all published placers in runtime and performance on ISPD 2005 and 2006 benchmarks.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131946316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs 三维集成电路中硅通孔直流电流拥挤及其对电源完整性的影响分析
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228391
Xin Zhao, M. Scheuermann, S. Lim
{"title":"Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs","authors":"Xin Zhao, M. Scheuermann, S. Lim","doi":"10.1145/2228360.2228391","DOIUrl":"https://doi.org/10.1145/2228360.2228391","url":null,"abstract":"Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and power wire segments as single resistors, which cannot capture the detailed current distribution and may miss trouble spots associated with current crowding. This paper studies DC current crowding and its impact on 3D power integrity. First, we explore the current density distribution within a TSV and its power wire connections. Second, we build and validate effective TSV models for current density distributions. Finally, these models are integrated with global power wires for detailed chip-scale power grid analysis.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124231883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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