DAC Design Automation Conference 2012最新文献_第7页

Worst-case execution time analysis for parallel run-time monitoring 并行运行时监控的最坏情况执行时间分析

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228435

Daniel Lo, G. Suh

引用次数: 4

Avoiding game over: Bringing design to the next level 避免游戏结束:将设计带入下一个阶段

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228472

Ofer Shacham, Sameh Galal, S. Sankaranarayanan, Megan Wachs, J. Brunhaver, A. Vassiliev, M. Horowitz, Andrew Danowitz, W. Qadeer, S. Richardson

{"title":"Avoiding game over: Bringing design to the next level","authors":"Ofer Shacham, Sameh Galal, S. Sankaranarayanan, Megan Wachs, J. Brunhaver, A. Vassiliev, M. Horowitz, Andrew Danowitz, W. Qadeer, S. Richardson","doi":"10.1145/2228360.2228472","DOIUrl":"https://doi.org/10.1145/2228360.2228472","url":null,"abstract":"Technology scaling has created a catch-22: technology now can do almost anything we want, but the NRE design costs are so high, that almost no one can afford to use it. Our current situation is reminiscent of the 1980's, when only a few companies could afford to produce custom silicon. Synthesis and placement and routing tools changed this, by providing modular tools with well defined interfaces that codified designer knowledge about the physical design of chips. Now we need a new set of tools that can codify designer knowledge about how to construct software, hardware, and validation to again enable application designers to produce chips. Researchers are developing methodologies that allow users to create hardware constructors, or generators. These include Genesis 2, which extends SystemVerilog and enables the designer to encode hierarchical system construction procedu-rally. To demonstrate some of the capabilities that these languages and tools provide, we describe FPGen, a complete floating point generator written in Genesis 2, that also generates the needed validation collateral and hints for the backend processes.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116974320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

Regaining throughput using completion detection for error-resilient, near-threshold logic 使用完成检测恢复吞吐量的错误弹性，近阈值逻辑

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228535

Joseph Crop, R. Pawlowski, P. Chiang

引用次数: 5

Instruction scheduling for reliability-aware compilation 面向可靠性感知编译的指令调度

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228601

Semeen Rehman, M. Shafique, J. Henkel

引用次数: 43

Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces 使用宽I/O接口的共享内存3d - mpsoc中具有成本效益的缓冲区大小

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228427

Sahar Foroutan, Abbas Sheibanyrad, F. Pétrot

引用次数: 5

Identification of recovered ICs using fingerprints from a light-weight on-chip sensor 使用轻量级片上传感器的指纹识别回收的ic

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228486

Xuehui Zhang, Nicholas Tuzzio, M. Tehranipoor

引用次数: 77

A metric for layout-friendly microarchitecture optimization in high-level synthesis 高级合成中布局友好型微架构优化的度量

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228587

J. Cong, B. Liu

引用次数: 7

Specification and synthesis of hardware checkpointing and rollback mechanisms 硬件检查点和回滚机制的规范和综合

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228585

C. Chan, Daniel Schwartz-Narbonne, D. Sethi, S. Malik

引用次数: 6

Test-data volume optimization for diagnosis 用于诊断的测试数据量优化

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228462

Hongfei Wang, O. Poku, Xiaochun Yu, Sizhe Liu, Ibrahima Komara, R. D. Blanton

{"title":"Test-data volume optimization for diagnosis","authors":"Hongfei Wang, O. Poku, Xiaochun Yu, Sizhe Liu, Ibrahima Komara, R. D. Blanton","doi":"10.1145/2228360.2228462","DOIUrl":"https://doi.org/10.1145/2228360.2228462","url":null,"abstract":"Test data collection for a failing integrated circuit (IC) can be very expensive and time consuming. Many companies now collect a fix amount of test data regardless of the failure characteristics. As a result, limited data collection could lead to inaccurate diagnosis, while an excessive amount increases the cost not only in terms of unnecessary test data collection but also increased cost for test execution and data-storage. In this work, the objective is to develop a method for predicting the precise amount of test data necessary to produce an accurate diagnosis. By analyzing the failing outputs of an IC during its actual test, the developed method dynamically determines which failing test pattern to terminate testing, producing an amount of test data that is sufficient for an accurate diagnosis analysis. The method leverages several statistical learning techniques, and is evaluated using actual data from a population of failing chips and five standard benchmarks. Experiments demonstrate that test-data collection can be reduced by >; 30% (as compared to collecting the full-failure response) while at the same time ensuring >;90% diagnosis accuracy. Prematurely terminating test-data collection at fixed levels (e.g., 100 failing bits) is also shown to negatively impact diagnosis accuracy.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121679761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 48

Synchronization for hybrid MPSoC full-system simulation 混合MPSoC全系统仿真的同步

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228383

L. Murillo, Juan Fernando Eusse Giraldo, Jovana Jovic, S. Yakoushkin, R. Leupers, G. Ascheid

引用次数: 13