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DAC Design Automation Conference 2012最新文献

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Design challenges for secure implantable medical devices 安全植入式医疗设备的设计挑战
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228364
W. Burleson, Shane S. Clark, Benjamin Ransford, Kevin Fu
{"title":"Design challenges for secure implantable medical devices","authors":"W. Burleson, Shane S. Clark, Benjamin Ransford, Kevin Fu","doi":"10.1145/2228360.2228364","DOIUrl":"https://doi.org/10.1145/2228360.2228364","url":null,"abstract":"Implantable medical devices, or IMDs, are increasingly being used to improve patients' medical outcomes. Designers of IMDs already balance safety, reliability, complexity, power consumption, and cost. However, recent research has demonstrated that designers should also consider security and data privacy to protect patients from acts of theft or malice, especially as medical technology becomes increasingly connected to other systems via wireless communications or the Internet. This survey paper summarizes recent work on IMD security. It discusses sound security principles to follow and common security pitfalls to avoid. As trends in power efficiency, sensing, wireless systems and bio-interfaces make possible new and improved IMDs, they also underscore the importance of understanding and addressing security and privacy concerns in an increasingly connected world.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"414 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123392124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 141
Communication-aware mapping of KPN applications onto heterogeneous MPSoCs KPN应用到异构mpsoc的通信感知映射
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228597
J. Castrillón, Andreas Tretter, R. Leupers, G. Ascheid
{"title":"Communication-aware mapping of KPN applications onto heterogeneous MPSoCs","authors":"J. Castrillón, Andreas Tretter, R. Leupers, G. Ascheid","doi":"10.1145/2228360.2228597","DOIUrl":"https://doi.org/10.1145/2228360.2228597","url":null,"abstract":"Kahn Process Networks (KPNs) are a widely accepted programming model for MPSoCs. Existing KPN mapping techniques mainly focus on assigning processes to processors. However, with embedded interconnect becoming more complex, communication has started to play an equally important role to that of computation. This paper presents a new KPN mapping algorithm that addresses communication and computation jointly. The algorithm is tested on two platforms with real applications and with randomly generated KPNs. We show that the algorithm finds solutions in situations where bare process mapping fails. It also reduced the average application makespan considerably when compared to previous heuristics.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"9 3-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130580689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
Quick detection of difficult bugs for effective post-silicon validation 快速检测困难的错误，有效的后硅验证
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228461
David C. Lin, Ted Hong, F. Fallah, N. Hakim, S. Mitra
{"title":"Quick detection of difficult bugs for effective post-silicon validation","authors":"David C. Lin, Ted Hong, F. Fallah, N. Hakim, S. Mitra","doi":"10.1145/2228360.2228461","DOIUrl":"https://doi.org/10.1145/2228360.2228461","url":null,"abstract":"We present a new technique for systematically creating postsilicon validation tests that quickly detect bugs in processor cores and uncore components (cache controllers, memory controllers, on-chip networks) of multi-core System on Chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation approaches. In addition, we provide a list of realistic bug scenarios abstracted from “difficult” bugs that occurred in commercial multi-core SoCs. Our results for an OpenSPARC T2-like multi-core SoC demonstrate: 1. Error detection latencies of “typical” post-silicon validation tests can be very long, up to billions of clock cycles, especially for bugs in uncore components. 2. Our new technique shortens error detection latencies by several orders of magnitude to only a few hundred cycles for most bug scenarios. 3. Our new technique enables 2-fold increase in bug coverage. An important feature of our technique is its software-only implementation without any hardware modification. Hence, it is readily applicable to existing designs.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128871411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Reliable computing with ultra-reduced instruction set co-processors 使用超精简指令集协处理器进行可靠计算
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228485
Aravindkumar Rajendiran, S. Ananthanarayanan, Hiren D. Patel, Mahesh V. Tripunitara, S. Garg
{"title":"Reliable computing with ultra-reduced instruction set co-processors","authors":"Aravindkumar Rajendiran, S. Ananthanarayanan, Hiren D. Patel, Mahesh V. Tripunitara, S. Garg","doi":"10.1145/2228360.2228485","DOIUrl":"https://doi.org/10.1145/2228360.2228485","url":null,"abstract":"This work presents a method to reliably perform computations in the presence of hard faults arising from aggressive technology scaling, and design defects from human error. Our method is based on an observation that a single Turing-complete instruction can mirror the semantics of any other instruction. One such instruction is the subleq instruction, which has been used for instructional purposes in the past. We find that the scope for using such a Turing-complete instruction is far greater, and in this paper, we present its applicability to fault tolerance. In particular, we extend a MIPS processor with a co-processor (called ultra-reduced instruction set co-processor - URISC) that implements the subleq instruction. We use the URISC to execute sequences of subleq that are semanti-cally equivalent to the faulty instructions. We formally prove this, and implement the translations in the back-end of the LLVM compiler. We generate binaries for our hardware prototype called MIPS-URISC, which we synthesize and execute on an Altera FPGA. Our experiments indicate the performance and area overheads, and the efficacy of the proposed approach.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133792013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Fast nonlinear model order reduction via associated transforms of high-order Volterra transfer functions 通过高阶Volterra传递函数的关联变换快速非线性模型降阶
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228415
Yang Zhang, Haotian Liu, Qing Wang, N. Fong, N. Wong
{"title":"Fast nonlinear model order reduction via associated transforms of high-order Volterra transfer functions","authors":"Yang Zhang, Haotian Liu, Qing Wang, N. Fong, N. Wong","doi":"10.1145/2228360.2228415","DOIUrl":"https://doi.org/10.1145/2228360.2228415","url":null,"abstract":"We present a new and fast way of computing the projection matrices serving high-order Volterra transfer functions in the context of (weakly and strongly) nonlinear model order reduction. The novelty is to perform, for the first time, the association of multivariate (Laplace) variables in high-order multiple-input multiple-output (MIMO) transfer functions to generate the standard single-s transfer functions. The consequence is obvious: instead of finding projection subspaces about every si, only that about a singles is required. This translates into drastic saving in computation and memory, and much more compact reduced-order nonlinear models, without compromising any accuracy.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134192676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Courteous cache sharing: Being nice to others in capacity management 礼貌共享缓存:在容量管理中善待他人
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228482
Akbar Sharifi, Shekhar Srikantaiah, M. Kandemir, M. J. Irwin
{"title":"Courteous cache sharing: Being nice to others in capacity management","authors":"Akbar Sharifi, Shekhar Srikantaiah, M. Kandemir, M. J. Irwin","doi":"10.1145/2228360.2228482","DOIUrl":"https://doi.org/10.1145/2228360.2228482","url":null,"abstract":"This paper proposes a cache management scheme for multiprogrammed, multithreaded applications, with the objective of obtaining maximum performance for both individual applications and the multithreaded workload mix. In this scheme, each individual application's performance is improved by increasing the priority of its slowest thread, while the overall system performance is improved by ensuring that each individual application's performance benefit does not come at the cost of a significant degradation to other application's threads that are sharing the same cache. Averaged over six workloads, our shared cache management scheme improves the performance of the combination of applications by 18%. These improvements across applications in each mix are also fair, as indicated by average fair speedup improvements of 10% across the threads of each application (averaged over all the workloads).","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134241797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Biomedical electronics serving as physical environmental and emotional watchdogs 生物医学电子学充当物理、环境和情感的看门狗
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228362
R. Lauwereins
{"title":"Biomedical electronics serving as physical environmental and emotional watchdogs","authors":"R. Lauwereins","doi":"10.1145/2228360.2228362","DOIUrl":"https://doi.org/10.1145/2228360.2228362","url":null,"abstract":"Over forty years of happy CMOS scaling brought the room-sized super-computer for the nerds into everyone's pocket, literally connecting every-body on earth. In an economy which is based on double digit growth, the obvious next step is to connect everything on earth. This move redirects the focus from electronics-for-infotainment to electronics helping to solve the mounting societal challenges our earth faces: better and more affordable health care for everyone, safer and more efficient transportation, cleaner and more sustainable environment. Realizing this requires abandoning the traditional keyboard/screen user interface to make the electronic devices autonomous, independent from a human in the loop, and to provide its services hidden in the background. In this paper, I will first explain why in the background operating electronics recently became feasible in the form of autonomous wireless sensor nodes. Next, I will present a technology roadmap, ranging from sensors measuring physical phenomena, via environmental sensors that combine physical with chemical monitoring, to ultimately emotional sensors that provide instantaneous and objective information about one's emotions. For those worrying about \"big brother\" possibilities, I will end the presentation with a concrete use case for psychiatric drug approval.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134368407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Write performance improvement by hiding R drift latency in phase-change RAM 通过在相变RAM中隐藏R漂移延迟来提高写入性能
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228520
Youngsik Kim, S. Yoo, Sunggu Lee
{"title":"Write performance improvement by hiding R drift latency in phase-change RAM","authors":"Youngsik Kim, S. Yoo, Sunggu Lee","doi":"10.1145/2228360.2228520","DOIUrl":"https://doi.org/10.1145/2228360.2228520","url":null,"abstract":"Phase-change RAM (PRAM) is considered to be one of the most promising candidates to complement or replace DRAM in the near future. However, it is imperative to overcome the limitations of PRAM, especially, long write latency for its widespread applications. R drift latency occupies a significant portion in PRAM write latency thereby adversely affecting system performance. In this paper, we propose a novel method called write status holding register (WSHR) to reduce the write latency due to R drift latency. The WSHR allows for non-blocking accesses to PRAM during R drift latency thereby improving system performance. Our experiments with SPEC benchmarks show that the proposed WSHR gives 53.6%~0% performance improvements in the hybrid DRAM/PRAM main memory (256MB DRAM and 14nm PRAM).","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132017176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Near-threshold voltage (NTV) design — Opportunities and challenges 近阈值电压(NTV)设计-机遇与挑战
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228572
Himanshu Kaul, M. Anders, S. Hsu, A. Agarwal, R. Krishnamurthy, S. Borkar
{"title":"Near-threshold voltage (NTV) design — Opportunities and challenges","authors":"Himanshu Kaul, M. Anders, S. Hsu, A. Agarwal, R. Krishnamurthy, S. Borkar","doi":"10.1145/2228360.2228572","DOIUrl":"https://doi.org/10.1145/2228360.2228572","url":null,"abstract":"Moore's Law will continue providing abundance of transistors for integration, only to be limited by the energy consumption. Near threshold voltage (NTV) operation has potential to improve energy efficiency by an order of magnitude. We discuss design techniques necessary for reliable operation over a wide range of supply voltage - from nominal down to subthreshold region. The system designed for NTV can dynamically select modes of operation, from high performance, to high energy efficiency, to the lowest power.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129459949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 265
SAGA: SystemC acceleration on GPU architectures SAGA: GPU架构上的系统加速
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228382
S. Vinco, Debapriya Chatterjee, V. Bertacco, F. Fummi
{"title":"SAGA: SystemC acceleration on GPU architectures","authors":"S. Vinco, Debapriya Chatterjee, V. Bertacco, F. Fummi","doi":"10.1145/2228360.2228382","DOIUrl":"https://doi.org/10.1145/2228360.2228382","url":null,"abstract":"SystemC is a widespread language for HW/SW system simulation and design exploration, and thus a key development platform in embedded system design. However, the growing complexity of SoC designs is having an impact on simulation performance, leading to limited SoC exploration potential, which in turns affects development and verification schedules and time-to-market for new designs. Previous efforts have attempted to parallelize SystemC simulation, targeting both multiprocessors and GPUs. However, for practical designs, those approaches fall far short of satisfactory performance. This paper proposes SAGA, a novel simulation approach that fully exploits the intrinsic parallelism of RTL SystemC descriptions, targeting GPU platforms. By limiting synchronization events with ad-hoc static scheduling and separate independent dataflows, we shows that we can simulate complex SystemC descriptions up to 16 times faster than traditional simulators.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"318 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133280559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
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