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DAC Design Automation Conference 2012最新文献

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Humans for EDA and EDA for humans 人类为EDA, EDA为人类
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228492
V. Bertacco
{"title":"Humans for EDA and EDA for humans","authors":"V. Bertacco","doi":"10.1145/2228360.2228492","DOIUrl":"https://doi.org/10.1145/2228360.2228492","url":null,"abstract":"Two misconceptions have been plaguing the electronic design automation (EDA) industry for decades: i) EDA solutions scale to larger complexities at an insufficient rate to keep pace with improvements in silicon designs; and ii) since EDA applications target silicon chip developments, the growth of EDA as an industry is bounded by the growth of the semiconductor industry. With this paper we address these misconceptions and we argue that they can both be overcome. To this end, we overview a number of initial studies highlighting possible directions that EDA can pursue to (i) break off from its traditional ways of scaling solutions and applications to larger complexity, that is, by developing better heuristics for its complex algorithms. (ii) We also discuss alternative domains where EDA technology can be applied, beyond that of silicon design, so that the semiconductor industry is no longer the limit of EDA growth.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132127596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Extracting design information from natural language specifications 从自然语言规范中提取设计信息
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228591
I. Harris
{"title":"Extracting design information from natural language specifications","authors":"I. Harris","doi":"10.1145/2228360.2228591","DOIUrl":"https://doi.org/10.1145/2228360.2228591","url":null,"abstract":"Natural language specifications are the first concrete behavioral description which is the basis for any manually generated formal behavioral model. Natural language is preferred as the initial description method mainly because it is much simpler for a designer to use than existing hardware description languages. The focus of this project is the extraction of behavioral information from a natural language specification to generate a formal behavioral description with clear and unambiguous semantics. In the initial effort presented here, we employ semantic parsing to identify key information describing bus transactions in the natural language specification. The identified information is used to generate Verilog tasks which embody bus transactions. To our knowledge, the work presented here is the first attempt to generate simulatable Verilog from natural language descriptions.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133487433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Near-threshold operation for power-efficient computing? It depends… 接近阈值操作的节能计算?这取决于……
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228573
Leland Chang, W. Haensch
{"title":"Near-threshold operation for power-efficient computing? It depends…","authors":"Leland Chang, W. Haensch","doi":"10.1145/2228360.2228573","DOIUrl":"https://doi.org/10.1145/2228360.2228573","url":null,"abstract":"While it has long been argued that near-threshold (~0.5V) operation of CMOS technologies can dramatically improve power efficiency, widespread application of such low voltage operation to VLSI systems has yet to materialize. This is due in part to practical system workload demands, in which single-thread performance needs can limit strategies to improve parallelizeable throughput performance, but also due to barriers in the ability of supporting hardware to counter variability and reliability concerns while maintaining power efficiency throughout the system. This paper describes the issues on which the realization of near-threshold computing depends to explain why this strategy is not yet pervasive today. However, recent advancements across the spectrum of system design - including heterogeneous architectures, transistor and memory technologies, power delivery, packaging, and I/O - suggest that as the market for throughput performance grows, hardware technologies may soon become available to practically harness the promise of near-threshold operation.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132450096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Accurate process-hotspot detection using critical design rule extraction 使用关键设计规则提取精确的过程热点检测
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228576
Yen-Ting Yu, Y. Chan, S. Sinha, I. Jiang, C. Chiang
{"title":"Accurate process-hotspot detection using critical design rule extraction","authors":"Yen-Ting Yu, Y. Chan, S. Sinha, I. Jiang, C. Chiang","doi":"10.1145/2228360.2228576","DOIUrl":"https://doi.org/10.1145/2228360.2228576","url":null,"abstract":"In advanced fabrication technology, the sub-wavelength lithography gap causes unwanted layout distortions. Even if a layout passes design rule checking (DRC), it still might contain process hotspots, which are sensitive to the lithographic process. Hence, process-hotspot detection has become a crucial issue. In this paper, we propose an accurate process-hotspot detection framework. Unlike existing DRC-based works, we extract only critical design rules to express the topological features of hotspot patterns. We adopt a two-stage filtering process to locate all hotspots accurately and efficiently. Compared with state-of-the-art DRC-based works, our results show that our approach can reach 100% success rate with significant speedups.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129326879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 77
Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU 基于混合DRAM/ pram的单片CPU/GPU主存
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228519
Dongki Kim, Sungkwang Lee, Jaewoong Chung, Daehyun Kim, Dong Hyuk Woo, S. Yoo, Sunggu Lee
{"title":"Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU","authors":"Dongki Kim, Sungkwang Lee, Jaewoong Chung, Daehyun Kim, Dong Hyuk Woo, S. Yoo, Sunggu Lee","doi":"10.1145/2228360.2228519","DOIUrl":"https://doi.org/10.1145/2228360.2228519","url":null,"abstract":"Single-chip CPU/GPU architecture is being adopted in high-end (embedded) systems, e.g., smartphones and tablet PCs. Main memory subsystem is expected to consist of hybrid DRAM and phase-change RAM (PRAM) due to the difficulties in DRAM scaling. In this work, we address the performance optimization of the hybrid DRAM/PRAM main memory for single chip CPU/GPU. Based on the tight requirements of low latency from CPU and the relative tolerance to long latency from GPU, DRAM is first allocated to CPU while PRAM with longer write latency is allocated to GPU. Then, in order to improve the write performance of GPU traffic, we propose (1) an in-DRAM write buffer to accommodate GPU write traffics, (2) dynamic hot data management to improve the efficiency of write buffer, (3) runtime-adaptive adjustment of write buffer size to meet the given CPU performance bound, and (4) CPU-aware DRAM access scheduling to give low latency to CPU traffics. The experiments show that the proposed method gives 1.02~44.2 times performance improvement in GPU performance with modest (negligible) CPU performance overhead (when compute-intensive CPU programs run).","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"748 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116101332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
An efficient algorithm for multi-layer obstacle-avoiding rectilinear Steiner tree construction 多层避障直线斯坦纳树构造的一种高效算法
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228471
Chih-Hung Liu, I-Che Chen, Der-Tsai Lee
{"title":"An efficient algorithm for multi-layer obstacle-avoiding rectilinear Steiner tree construction","authors":"Chih-Hung Liu, I-Che Chen, Der-Tsai Lee","doi":"10.1145/2228360.2228471","DOIUrl":"https://doi.org/10.1145/2228360.2228471","url":null,"abstract":"We consider the multi-layer obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) problem and propose a reduction to transform a multi-layer instance into a 3D instance. Based on the reduction we apply computational geometry techniques to develop an efficient algorithm, utilizing existing OARSMT heuristics. Experimental results show that our algorithm provides a solution with excellent quality and has a significant speed-up compared to previously known results.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116120311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Software controlled cell bit-density to improve NAND flash lifetime 软件控制单元位密度，提高NAND闪存寿命
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228404
Xavier Jimenez, D. Novo, P. Ienne
{"title":"Software controlled cell bit-density to improve NAND flash lifetime","authors":"Xavier Jimenez, D. Novo, P. Ienne","doi":"10.1145/2228360.2228404","DOIUrl":"https://doi.org/10.1145/2228360.2228404","url":null,"abstract":"Hybrid flash architectures combine static partitions in Single Level Cell (SLC) mode with partitions in Multi Level Cell (MLC) mode. Compared to MLC-only solutions, the former exploits fast and short random writes while the latter brings large capacity. On the whole, one achieves an overall tangible performance improvement for a moderate extra cost. Yet, device lifetime is an important aspect often overlooked. In this paper, we show how a dynamic SLC-MLC scheme provides significant lifetime improvement (up to 10 times) at no cost compared to any classic static SLC-MLC partitioning based on any state of the art Flash Translation Layer policy.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123534397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
The HELIX project: Overview and directions HELIX项目:概述和方向
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228412
Simone Campanoni, Timothy M. Jones, G. Holloway, Gu-Yeon Wei, D. Brooks
{"title":"The HELIX project: Overview and directions","authors":"Simone Campanoni, Timothy M. Jones, G. Holloway, Gu-Yeon Wei, D. Brooks","doi":"10.1145/2228360.2228412","DOIUrl":"https://doi.org/10.1145/2228360.2228412","url":null,"abstract":"Parallelism has become the primary way to maximize processor performance and power efficiency. But because creating parallel programs by hand is difficult and prone to error, there is an urgent need for automatic ways of transforming conventional programs to exploit modern multicore systems. The HELIX compiler transformation is one such technique that has proven effective at parallelizing individual sequential programs automatically for a real six-core processor. We describe that transformation in the context of the broader HELIX research project, which aims to optimize the throughput of a multicore processor by coordinated changes in its architecture, its compiler, and its operating system. The goal is to make automatic parallelization mainstream in multiprogramming settings through adaptive algorithms for extracting and tuning thread-level parallelism.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122368121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Exploiting narrow-width values for process variationtolerant 3-D microprocessors 利用窄宽度值的过程变化容忍三维微处理器
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228581
J. Kong, S. Chung
{"title":"Exploiting narrow-width values for process variationtolerant 3-D microprocessors","authors":"J. Kong, S. Chung","doi":"10.1145/2228360.2228581","DOIUrl":"https://doi.org/10.1145/2228360.2228581","url":null,"abstract":"Process variation is a challenging problem in 3D microprocessors, since it adversely affects performance, power, and reliability of 3D microprocessors, which in turn results in yield losses. In this paper, we propose a novel architectural scheme that exploits the narrow-width value for yield improvement of last-level caches in 3D microprocessors. In a energy-/performance-efficient manner, our proposed scheme improves cache yield by 58.7% and 17.3% compared to the baseline and the naïve way-reduction scheme (that simply discards faulty cache lines), respectively.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124875672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Non-uniform multilevel analog routing with matching constraints 具有匹配约束的非均匀多电平模拟路由
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228458
H. Ou, Hsing-Chih Chang Chien, Yao-Wen Chang
{"title":"Non-uniform multilevel analog routing with matching constraints","authors":"H. Ou, Hsing-Chih Chang Chien, Yao-Wen Chang","doi":"10.1145/2228360.2228458","DOIUrl":"https://doi.org/10.1145/2228360.2228458","url":null,"abstract":"Symmetry, topology-matching, and length-matching constraints are three major routing considerations to improve the performance of an analog circuit. Symmetry constraints are specified to route matched nets symmetrically with respect to some common axes. Topology-matching constraints are commonly imposed on critical yet asymmetry nets with the same number of bends, vias, and wirelength. Length-matching constraints are specified to route the nets which have limited resources with the same wirelength. These three constraints can reduce current mismatches and unwanted electrical effects between two critical nets. In this paper, we propose the first work to simultaneously consider the three constraints for analog routing while minimizing total wirelength, bend numbers, via counts, and coupling noise at the same time. We first present an integer linear programming (ILP) formulation to simultaneously consider the three constraints for analog routing, and employ effective reduction techniques to further reduce the numbers of ILP variables and constraints. Then, a non-uniform multilevel routing framework is presented to enhance the performance of our routing algorithm. Experimental results show that our approach can obtain better routing results and satisfy all specified routing constraints while optimizing circuit performance.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130420756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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