利用窄宽度值的过程变化容忍三维微处理器

J. Kong, S. Chung
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引用次数: 12

摘要

在3D微处理器中,工艺变化是一个具有挑战性的问题,因为它会对3D微处理器的性能、功耗和可靠性产生不利影响,从而导致良率损失。在本文中,我们提出了一种新的架构方案,利用窄宽度值来提高三维微处理器中最后一级缓存的良率。在能源/性能高效的方式下,与基线和naïve方式减少方案(简单地丢弃有故障的缓存线路)相比,我们提出的方案分别提高了58.7%和17.3%的缓存产量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Exploiting narrow-width values for process variationtolerant 3-D microprocessors
Process variation is a challenging problem in 3D microprocessors, since it adversely affects performance, power, and reliability of 3D microprocessors, which in turn results in yield losses. In this paper, we propose a novel architectural scheme that exploits the narrow-width value for yield improvement of last-level caches in 3D microprocessors. In a energy-/performance-efficient manner, our proposed scheme improves cache yield by 58.7% and 17.3% compared to the baseline and the naïve way-reduction scheme (that simply discards faulty cache lines), respectively.
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