DAC Design Automation Conference 2012最新文献

Clock tree synthesis with methodology of re-use in 3D IC 三维集成电路中时钟树的合成与复用方法

DAC Design Automation Conference 2012 Pub Date : 2014-04-01 DOI: 10.1145/2567668

Fu-Wei Chen, TingTing Hwang

引用次数: 6

Algorithms and data structures for fast and good VLSI routing 快速和良好的VLSI路由算法和数据结构

DAC Design Automation Conference 2012 Pub Date : 2013-03-01 DOI: 10.1145/2442087.2442103

Michael Gester, D. Müller, T. Nieberg, Christian Panten, C. Schulte, J. Vygen

引用次数: 42

Circuit and system design guidelines for ultra-low power sensor nodes 超低功耗传感器节点的电路和系统设计指南

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228548

Yoonmyung Lee, Dongmin Yoon, Yejoong Kim, D. Blaauw, D. Sylvester

引用次数: 22

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs 基于tsv的3D集成电路热机械应力和可靠性的芯片/封装联合分析

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228419

Moongon Jung, D. Pan, S. Lim

引用次数: 20

Security analysis of logic obfuscation 逻辑混淆的安全分析

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228377

Jeyavijayan Rajendran, Youngok Pino, O. Sinanoglu, R. Karri

引用次数: 412

Simultaneous flare level and flare variation minimization with dummification in EUVL EUVL中同时耀斑电平和耀斑变化的最小化

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228578

Shao-Yun Fang, Yao-Wen Chang

{"title":"Simultaneous flare level and flare variation minimization with dummification in EUVL","authors":"Shao-Yun Fang, Yao-Wen Chang","doi":"10.1145/2228360.2228578","DOIUrl":"https://doi.org/10.1145/2228360.2228578","url":null,"abstract":"Extreme Ultraviolet Lithography (EUVL) is one of the most promising Next Generation Lithography (NGL) technologies. Due to the surface roughness of the optical system used in EUVL, the rather high level of flare (i.e., scattered light) becomes one of the most critical issues in EUVL. In addition, the layout density non-uniformity and the flare periphery effect (the flare distribution at the periphery is much different from that in the center of a chip) also induce a large flare variation within a layout. Both of the high flare level and the large flare variation could worsen the control of critical dimension (CD) uniformity. Dummification (i.e., tiling or dummy fill) is one of the flare compensation strategies to reduce the flare level and the flare variation for the process with a clear-field mask in EUVL. However, existing dummy fill algorithms for Chemical-Mechanical Polishing (CMP) are not adequate for the flare mitigation problem in EUVL due to the flare periphery effect. This paper presents the first work that solves the flare mitigation problem in EUVL with a specific dummification algorithm flow considering global flare distribution. The dummification process is guided by dummy demand maps, which are generated by using a quasi-inverse lithography technique. In addition, an error-controlled fast flare map computation technique is proposed and integrated into our algorithm to further improve the efficiency without loss of computation accuracy. Experimental results show that our flow can effectively and efficiently reduce the flare level and the flare variation, which may contribute to the better control of CD uniformity.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116529842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

A methodology for energy-quality tradeoff using imprecise hardware 一种使用不精确硬件进行能源质量权衡的方法

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228450

Jiawei Huang, J. Lach, G. Robins

引用次数: 89

Integrated biosensors for personalized medicine 用于个性化医疗的集成生物传感器

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228363

G. Micheli, C. Boero, C. Baj-Rossi, I. Taurino, S. Carrara

引用次数: 3

Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse 暗硅有用吗?驾驭即将到来的黑暗硅天启的四骑士

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228567

M. Taylor

{"title":"Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse","authors":"M. Taylor","doi":"10.1145/2228360.2228567","DOIUrl":"https://doi.org/10.1145/2228360.2228567","url":null,"abstract":"Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utilization wall forces designers to ensure that, at any point in time, large fractions of their chips are effectively dark or dim silicon, i.e., either idle or significantly underclocked. As exponentially larger fractions of a chip's transistors become dark, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift is driving a new class of architectural techniques that “spend” area to “buy” energy efficiency. All of these techniques seek to introduce new forms of heterogeneity into the computational stack. We envision that ultimately we will see widespread use of specialized architectures that leverage these techniques in order to attain orders-of-magnitude improvements in energy efficiency. However, many of these approaches also suffer from massive increases in complexity. As a result, we will need to look towards developing pervasively specialized architectures that insulate the hardware designer and the programmer from the underlying complexity of such systems. In this paper, I discuss four key approaches - the four horsemen - that have emerged as top contenders for thriving in the dark silicon age. Each class carries with its virtues deep-seated restrictions that requires a careful understanding of the underlying tradeoffs and benefits.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123878386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 348

High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service 具有多种仲裁方案和服务质量的高基数自仲裁交换机结构

DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228432

Sudhir K. Satpathy, R. Das, R. Dreslinski, T. Mudge, D. Sylvester, D. Blaauw

引用次数: 9