Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU

Dongki Kim, Sungkwang Lee, Jaewoong Chung, Daehyun Kim, Dong Hyuk Woo, S. Yoo, Sunggu Lee
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引用次数: 28

Abstract

Single-chip CPU/GPU architecture is being adopted in high-end (embedded) systems, e.g., smartphones and tablet PCs. Main memory subsystem is expected to consist of hybrid DRAM and phase-change RAM (PRAM) due to the difficulties in DRAM scaling. In this work, we address the performance optimization of the hybrid DRAM/PRAM main memory for single chip CPU/GPU. Based on the tight requirements of low latency from CPU and the relative tolerance to long latency from GPU, DRAM is first allocated to CPU while PRAM with longer write latency is allocated to GPU. Then, in order to improve the write performance of GPU traffic, we propose (1) an in-DRAM write buffer to accommodate GPU write traffics, (2) dynamic hot data management to improve the efficiency of write buffer, (3) runtime-adaptive adjustment of write buffer size to meet the given CPU performance bound, and (4) CPU-aware DRAM access scheduling to give low latency to CPU traffics. The experiments show that the proposed method gives 1.02~44.2 times performance improvement in GPU performance with modest (negligible) CPU performance overhead (when compute-intensive CPU programs run).
基于混合DRAM/ pram的单片CPU/GPU主存
单芯片CPU/GPU架构正在高端(嵌入式)系统中被采用,例如智能手机和平板电脑。由于DRAM扩展困难,主存储器子系统预计将由混合DRAM和相变RAM (PRAM)组成。本文研究了单片CPU/GPU混合DRAM/PRAM主存的性能优化问题。基于对CPU低时延的严格要求和对GPU长时延的相对容忍度,首先将DRAM分配给CPU,将写时延较长的PRAM分配给GPU。然后,为了提高GPU流量的写性能,我们提出了(1)在DRAM中写入缓冲区以容纳GPU写流量,(2)动态热数据管理以提高写入缓冲区的效率,(3)运行时自适应调整写入缓冲区大小以满足给定的CPU性能边界,(4)CPU感知的DRAM访问调度以降低CPU流量的延迟。实验表明,该方法在CPU性能开销适中(可忽略不计)的情况下(当计算密集型CPU程序运行时),GPU性能提高了1.02~44.2倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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