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DAC Design Automation Conference 2012最新文献

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BLAST: Efficient computation of nonlinear delay sensitivities in electronic and biological networks using barycentric lagrange enabled transient adjoint analysis 利用重心拉格朗日支持的瞬态伴随分析有效计算电子和生物网络中的非线性延迟灵敏度
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228417
Arie Meir, J. Roychowdhury
{"title":"BLAST: Efficient computation of nonlinear delay sensitivities in electronic and biological networks using barycentric lagrange enabled transient adjoint analysis","authors":"Arie Meir, J. Roychowdhury","doi":"10.1145/2228360.2228417","DOIUrl":"https://doi.org/10.1145/2228360.2228417","url":null,"abstract":"Transient waveform sensitivities are useful in optimization and also provide direct insight into system metrics such as delay. We present a novel method for finding parametric waveform sensitivities that improves upon current transient adjoint methods, which suffer from quadratic complexity, by applying barycentric Lagrange interpolation to reduce computation to near linear in the time-interval of interest. We apply our technique to find sensitivities of a \"nonlinear\" Elmore-delay like metric in digital logic and biochemical pathway examples. Our technique achieves order-of-magnitude speedups over traditional adjoint and direct sensitivity computation.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130150529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation 用于硬件辅助软硬件协同仿真的非侵入式时序同步接口
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228384
Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, R. Tsay
{"title":"A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation","authors":"Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, R. Tsay","doi":"10.1145/2228360.2228384","DOIUrl":"https://doi.org/10.1145/2228360.2228384","url":null,"abstract":"This paper proposes using a non-intrusive timing synchronization interface approach to facilitate shared-data synchronization for fast and accurate hardware-assisted HW/SW co-simulation. Our synchronization interface device is specially designed for nontransparent components. With the device, we can systematically monitor shared-data accesses on a bus and control the progressing time of hardware-assisted components for fast and accurate system co-simulation. Experiments show that our approach is 10 to 140 times faster than the cycle-based hardware-assisted co-simulation approach.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130477235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
System verification of concurrent RTL modules by compositional path predicate abstraction 基于组合路径谓词抽象的并发RTL模块系统验证
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228422
J. Urdahl, D. Stoffel, Markus Wedler, W. Kunz
{"title":"System verification of concurrent RTL modules by compositional path predicate abstraction","authors":"J. Urdahl, D. Stoffel, Markus Wedler, W. Kunz","doi":"10.1145/2228360.2228422","DOIUrl":"https://doi.org/10.1145/2228360.2228422","url":null,"abstract":"A new methodology for formal system verification of System-on-Chip (SoC) designs is proposed. It does not only ensure correctness of the system-level models but also of the concrete implementation at the Register-Transfer-Level (RTL). For each SoC module at the RTL an abstract description is obtained by path predicate abstraction. Since this leads to time-abstract system models the main challenge is to deal with the concurrency between the individual RTL components. We propose a compositional scheme describing the communication between SoC modules independently of their individual processing speed. The composed abstract system is modeled as an asynchronous composition and can be verified using the SPIN model checker. We demonstrate the practical feasibility of our approach by a comprehensive case study based on Infineon's FPI Bus.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128892697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Cost-effective power delivery to support per-core voltage domains for power-constrained processors 具有成本效益的功率传输，支持功率受限处理器的每核电压域
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228372
H. Ghasemi, Abhishek A. Sinkar, M. Schulte, N. Kim
{"title":"Cost-effective power delivery to support per-core voltage domains for power-constrained processors","authors":"H. Ghasemi, Abhishek A. Sinkar, M. Schulte, N. Kim","doi":"10.1145/2228360.2228372","DOIUrl":"https://doi.org/10.1145/2228360.2228372","url":null,"abstract":"Per-core voltage domains can improve performance under a power constraint. Most commercial processors, however, only have one chip-wide voltage domain because splitting the voltage domain into per-core voltage domains and powering them with multiple off-chip voltage regulators (VRs) incurs a high cost for the platform and package designs. Although using on-chip switching VRs can be an alternative solution, integrating high-quality inductors and cores on the same chip has been a technical challenge. In this paper, we propose a cost-effective power delivery technique to support per-core voltage domains. Our technique is based on the observations that (i) core-to-core voltage variations are relatively small for most execution intervals when the voltages/frequencies are optimized to maximize performance under a power constraint and (ii) per-core power-gating devices augmented with small circuits can serve as low-cost VRs that can provide high efficiency in situations like (i). Our experimental results show that processors using our technique can achieve power efficiency as high as those using per-core on-chip switching VRs at much lower cost.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128897307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
The case for elastic operating system services in fos 在fos中使用弹性操作系统服务的案例
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228410
Lamia Youseff, Nathan Beckmann, H. Kasture, Charles Gruenwald, D. Wentzlaff, A. Agarwal
{"title":"The case for elastic operating system services in fos","authors":"Lamia Youseff, Nathan Beckmann, H. Kasture, Charles Gruenwald, D. Wentzlaff, A. Agarwal","doi":"10.1145/2228360.2228410","DOIUrl":"https://doi.org/10.1145/2228360.2228410","url":null,"abstract":"Given exponential scaling, it will not be long before chips with hundreds of cores are standard. For OS designers, this new trend in architectures provides a new opportunity to explore different research directions in scaling operating systems. The primary question facing OS designers over the next ten years will be: What is the correct design of OS services that will scale up to hundreds or thousands of cores, and adapt to the unprecedented variability in demand of the system resources? A fundamental research challenge addressed in this paper is to identify some characteristics of such a scalable OS service for next multicore and cloud computing chips. We argue that the OS services have to deploy elastic techniques to adapt to this variability at runtime. In this paper, we advocate for elastic OS service, illustrate their feasibility and effectiveness in meeting the variable demands through providing elastic technologies for OS services in the fos operating system. We furthermore showcase a prototype elastic file system service fos and illustrate its effectiveness in meeting variable demands.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121428171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A hybrid approach to cyber-physical systems verification 网络物理系统验证的混合方法
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228484
Pratyush Kumar, Dip Goswami, S. Chakraborty, A. Annaswamy, Kai Lampka, L. Thiele
{"title":"A hybrid approach to cyber-physical systems verification","authors":"Pratyush Kumar, Dip Goswami, S. Chakraborty, A. Annaswamy, Kai Lampka, L. Thiele","doi":"10.1145/2228360.2228484","DOIUrl":"https://doi.org/10.1145/2228360.2228484","url":null,"abstract":"We propose a performance verification technique for cyber-physical systems that consist of multiple control loops implemented on a distributed architecture. The architectures we consider are fairly generic and arise in domains such as automotive and industrial automation; they are multiple processors or electronic control units (ECUs) communicating over buses like FlexRay and CAN. Current practice involves analyzing the architecture to estimate worst-case end-to-end message delays and using these delays to design the control applications. This involves a significant amount of pessimism since the worst-case delays often occur very rarely. We show how to combine functional analysis techniques with model checking in order to derive a delay-frequency interface that quantifies the interleavings between messages with worst-case delays and those with smaller delays. In other words, we bound the frequency with which control messages might suffer the worst-case delay. We show that such a delay-frequency interface enables us to verify much tigher control performance properties compared to what would be possible with only worst-case delay bounds.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122433393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 71
Can EDA combat the rise of electronic counterfeiting? EDA能对抗电子假冒的兴起吗?
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228386
F. Koushanfar, Saverio Fazzari, C. McCants, William Bryson, Matthew Sale, P. Song, M. Potkonjak
{"title":"Can EDA combat the rise of electronic counterfeiting?","authors":"F. Koushanfar, Saverio Fazzari, C. McCants, William Bryson, Matthew Sale, P. Song, M. Potkonjak","doi":"10.1145/2228360.2228386","DOIUrl":"https://doi.org/10.1145/2228360.2228386","url":null,"abstract":"The Semiconductor Industry Associates (SIA) estimates that counterfeiting costs the US semiconductor companies $7.5B in lost revenue, and this is indeed a growing global problem. Repackaging the old ICs, selling the failed test parts, as well as gray marketing, are the most dominant counterfeiting practices. Can technology do a better job than lawyers? What are the technical challenges to be addressed? What EDA technologies will work: embedding IP protection measures in the design phase, developing rapid post-silicon certification, or counterfeit detection tools and methods?","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117112124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
Conforming the runtime inputs for hard real-time embedded systems 符合硬实时嵌入式系统的运行时输入
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228436
Kai Huang, Gang Chen, C. Buckl, A. Knoll
{"title":"Conforming the runtime inputs for hard real-time embedded systems","authors":"Kai Huang, Gang Chen, C. Buckl, A. Knoll","doi":"10.1145/2228360.2228436","DOIUrl":"https://doi.org/10.1145/2228360.2228436","url":null,"abstract":"Timing is an important concern when designing an embedded system. While lots of researches on hard real-time systems focus on design-time analysis, monitoring the corresponding runtime behaviors are seldom investigated. In this paper, we investigate the conformity problem for runtime inputs of a hard real-time system. We adopt the widely used arrival curve model which captures the worst/best-cases event arrivals in the time interval domain and propose an algorithm to on-the-fly evaluate the conformity of the system input w.r.t. given arrival curves. The developed algorithm is lightweight in terms of both computation and memory overheads, which is particularly suitable for resource-constrained embedded systems. We also provide proofs and an FPGA implementation to demonstrate the effectiveness of our approach.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128464746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Chisel: Constructing hardware in a Scala embedded language 凿:用Scala嵌入式语言构造硬件
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228584
J. Bachrach, Huy D. Vo, B. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, J. Wawrzynek, K. Asanović
{"title":"Chisel: Constructing hardware in a Scala embedded language","authors":"J. Bachrach, Huy D. Vo, B. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, J. Wawrzynek, K. Asanović","doi":"10.1145/2228360.2228584","DOIUrl":"https://doi.org/10.1145/2228360.2228584","url":null,"abstract":"In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. By embedding Chisel in the Scala programming language, we raise the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to map to either FPGAs or to a standard ASIC flow for synthesis. This paper presents Chisel, its embedding in Scala, hardware examples, and results for C++ simulation, Verilog emulation and ASIC synthesis.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"346 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114094188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 781
Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices 移动设备上视频流应用的保持质量的OLED动态电压缩放
DAC Design Automation Conference 2012 Pub Date : 2012-06-03 DOI: 10.1145/2228360.2228540
Xiang Chen, Jian Zheng, Yiran Chen, Mengying Zhao, C. Xue
{"title":"Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices","authors":"Xiang Chen, Jian Zheng, Yiran Chen, Mengying Zhao, C. Xue","doi":"10.1145/2228360.2228540","DOIUrl":"https://doi.org/10.1145/2228360.2228540","url":null,"abstract":"This paper developed a dynamic voltage scaling (DVS) technique for the power management of the OLED display on mobile devices in video streaming applications. An optimal voltage control scheme is proposed under input constraints. Fine-grained DVS technique is applied to maximize the power saving by leveraging the locality of the display content. The display quality is retained by monitoring structural-similarity-index (SSIM) during the optimization, subject to the hardware constraints like voltage regulator response time. Simulation results on four typical video test benchmarks show that the proposed technique saves 19.05%~49.05% OLED power on average while maintaining a high display quality (SSIM >; 0.98) all the time. The power saving efficiency of the proposed technique varies at different display resolutions, refresh rates, and display contents.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"22 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114102071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
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