A metric for layout-friendly microarchitecture optimization in high-level synthesis

Abstract

In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layout-friendly microarchitecture. A metric called spreading score is proposed to evaluate the layout-friendliness of microarchitectural netlist structures. For a piece of connected netlist, spreading score measures how far the components can be spread from each other with bounded length for every wire. The intuition is that components in a layout-friendly netlist (e.g., a mesh) can spread over the layout region without introducing long interconnects. We propose a semidefinite programming relaxation to allow efficient estimation of spreading score, and use it in a high-level synthesis tool. On a number of test cases, a normalized spreading score shows a stronger bias in favor of interconnect structures that have better timing after layout, compared to the widely used metric of total multiplexer inputs. We also justify our metric and motivate further study by relating spreading score to other metrics and problems for layout-friendly synthesis.