Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, S. Sunter, Yung-Fa Chou, D. Kwai
{"title":"Small delay testing for TSVs in 3-D ICs","authors":"Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, S. Sunter, Yung-Fa Chou, D. Kwai","doi":"10.1145/2228360.2228546","DOIUrl":"https://doi.org/10.1145/2228360.2228546","url":null,"abstract":"In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC. By changing the output inverter's threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault. SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124501933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jia Huang, Kai Huang, A. Raabe, C. Buckl, A. Knoll
{"title":"Towards fault-tolerant embedded systems with imperfect fault detection","authors":"Jia Huang, Kai Huang, A. Raabe, C. Buckl, A. Knoll","doi":"10.1145/2228360.2228398","DOIUrl":"https://doi.org/10.1145/2228360.2228398","url":null,"abstract":"Many state-of-the-art approaches on fault-tolerant system design make the simplifying assumption that all faults are detected within a certain time interval. However, based on a detailed experimental analysis, we observe that perfect fault detection is not only an impractical assumption but even if implementable also a suboptimal design decision. This paper presents an approach that takes imperfect fault detection into account. Novel analysis and optimization techniques are developed, which distinguish detectable and undetectable faults in the overall workflow. Besides synthesizing the task schedules, our approach also decides which of the available fault detectors is selected for each task instance. Experimental results show that our approach finds solutions with several orders of magnitude higher reliability than current approaches.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126149801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Path scheduling on digital microfluidic biochips","authors":"D. Grissom, P. Brisk","doi":"10.1145/2228360.2228367","DOIUrl":"https://doi.org/10.1145/2228360.2228367","url":null,"abstract":"Since the inception of digital microfluidics, the synthesis problems of scheduling, placement and routing have been performed offline (before runtime) due to their algorithmic complexity. However, with the increasing maturity of digital microfluidic research, online synthesis is becoming a realistic possibility that can bring new benefits in the areas of dynamic scheduling, control-flow, fault-tolerance and live-feedback. This paper contributes to the digital microfluidic synthesis process by introducing a fast, novel path-based scheduling algorithm that produces better schedules than list scheduler for assays with high fan-out; path scheduler computes schedules in milliseconds, making it suitable for both offline and online synthesis.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129678433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sangwon Seo, R. Dreslinski, M. Woh, Yongjun Park, C. Chakrabarti, S. Mahlke, D. Blaauw, T. Mudge
{"title":"Process variation in near-threshold wide SIMD architectures","authors":"Sangwon Seo, R. Dreslinski, M. Woh, Yongjun Park, C. Chakrabarti, S. Mahlke, D. Blaauw, T. Mudge","doi":"10.1145/2228360.2228536","DOIUrl":"https://doi.org/10.1145/2228360.2228536","url":null,"abstract":"Near-threshold operation has emerged as a competitive approach for energy-efficient architecture design. In particular, a combination of near-threshold circuit techniques and parallel SIMD computations achieves excellent energy efficiency for easy-to-parallelize applications. However, near-threshold operations suffer from delay variations due to increased process variability. This is exacerbated in wide SIMD architectures where the number of critical paths are multiplied by the SIMD width. This paper provides a systematic in-depth study of delay variations in near-threshold operations and shows that simple techniques such as structural duplication and supply voltage/frequency margining are sufficient to mitigate the timing variation problems in wide SIMD architectures at the cost of marginal area and power overhead.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124972147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"EDA for secure and dependable cybercars: Challenges and opportunities","authors":"F. Koushanfar, A. Sadeghi, Hervé Seudie","doi":"10.1145/2228360.2228402","DOIUrl":"https://doi.org/10.1145/2228360.2228402","url":null,"abstract":"Modern vehicles integrate a multitude of embedded hard realtime control functionalities, and a host of advanced information and entertainment (infotainment) features. The true paradigm shift for future vehicles (cybercars) is not only a result of this increasing plurality of subsystems and functions, but is also driven by the unprecedented levels of intra- and inter-car connections and communications as well as networking with external entities. Several new cybercar security and safety challenges simultaneously arise. On one hand, many challenges arise due to increasing system complexity as well as new functionalities that should jointly work on the existing legacy protocols and technologies; such systems are likely unable to warrant a fully secure and dependable system without afterthoughts. On the other hand, challenges arise due to the escalating number of interconnections among the realtime control functions, infotainment components, and the accessible surrounding external devices, vehicles, networks, and cloud services. The arrival of cybercars calls for novel abstractions, models, protocols, design methodologies, testing and evaluation tools to automate the integration and analysis of the safety and security requirements.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125085304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, N. Vijaykrishnan, R. Iyer, C. Das
{"title":"Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs","authors":"Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, N. Vijaykrishnan, R. Iyer, C. Das","doi":"10.1145/2228360.2228406","DOIUrl":"https://doi.org/10.1145/2228360.2228406","url":null,"abstract":"High density, low leakage and non-volatility are the attractive features of Spin-Transfer-Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a universal memory replacement in multi-core systems. However, STT-RAM suffers from high write latency and energy which has impeded its widespread adoption. To this end, we look at trading-off STT-RAM's non-volatility property (data-retention-time) to overcome these problems. We formulate the relationship between retention-time and write-latency, and find optimal retention-time for architecting an efficient cache hierarchy using STT-RAM. Our results show that, compared to SRAM-based design, our proposal can improve performance and energy consumption by 18% and 60%, respectively.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121616856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"What to do about the end of Moore's law, probably!","authors":"K. Palem, L. Avinash","doi":"10.1145/2228360.2228525","DOIUrl":"https://doi.org/10.1145/2228360.2228525","url":null,"abstract":"Computers process bits of information. A bit can take a value of 0 or 1, and computers process these bits through some physical mechanism. In the early days of electronic computers, this was done by electromechanical relays [28] which were soon replaced by vacuum tubes [6]. From the very beginning, these devices and the computers they were used to build were affected by concerns of reliability. For example, in a relatively recent interview with Presper Eckert [1] who co-designed ENIAC, widely believed to be the first electronic computer built, he notes: “we had a tube fail about every two days, and we could locate the problem within 15 minutes.”","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122618887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application of logic synthesis to the understanding and cure of genetic diseases","authors":"P. Lin, S. Khatri","doi":"10.1145/2228360.2228493","DOIUrl":"https://doi.org/10.1145/2228360.2228493","url":null,"abstract":"In the quest to understand and cure genetic diseases such as cancer, the fundamental approach being taken is undergoing a gradual change. It is becoming more acceptable to view these diseases as an engineering problem, and systems engineering approaches are becoming more accepted as a means to tackle genetic diseases. In this light, we believe that logic synthesis techniques can play a very important role. Several techniques from the field of logic synthesis can be adapted to assist in the arguably huge effort of modeling and controlling such diseases. The set of genes that control a particular genetic disease can be modeled as a Finite State Machine (FSM) called the Gene Regulatory Network (GRN). Important problems include (i) inferring the GRN from observed gene expression data from patients and (ii) assuming that such a GRN exists, determining the ”best” set of drugs so that the disease is ”maximally” cured. In this paper, we report initial results on the application of logic synthesis techniques that we have developed to address both these problems. In the first technique, we present Boolean Satisfiability (SAT) based approaches to infer the logical support of each gene that regulates melanoma, using gene expression data from patients of the disease. From the output of such a tool, biologists can construct targeted experiments to understand the logic functions that regulate a particular gene. The second technique assumes that the GRN is known, and uses a weighted partial Max-SAT formulation to find the set of drugs with the least side-effects, that steer the GRN state towards one that is closest to that of a healthy individual, in the context of colon cancer. Our group is currently exploring the application of several other logic techniques to a variety of related problems in this domain.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"13 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120856294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jing Guo, Fan Yang, S. Sinha, C. Chiang, Xuan Zeng
{"title":"Improved tangent space based distance metric for accurate lithographic hotspot classification","authors":"Jing Guo, Fan Yang, S. Sinha, C. Chiang, Xuan Zeng","doi":"10.1145/2228360.2228577","DOIUrl":"https://doi.org/10.1145/2228360.2228577","url":null,"abstract":"A distance metric of patterns is crucial to hotspot cluster analysis and classification. In this paper, we propose an improved tangent space based metric for pattern matching based hotspot cluster analysis and classification. The proposed distance metric is an important extension of the well-developed tangent space method in computer vision. It can handle patterns containing multiple polygons, while the traditional tangent space method can only deal with patterns with a single polygon. It inherits most of the advantages of the traditional tangent space method, e.g., it is easy to compute and is tolerant with small variations or shifts of the shapes. Compared with the existing distance metric based on XOR of hotspot patterns, the improved tangent space based distance metric can achieve up to 37.5% accuracy improvement with at most 4.3× computational cost in the context of cluster analysis. The improved tangent space based distance metric is a more reliable and accurate metric for hotspot cluster analysis and classification. It is more suitable for industry applications.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121330782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Generic low-cost characterization of VTH and mobility variations in LTPS TFTs for non-uniformity calibration of active-matrix OLED displays","authors":"G. Chaji, J. Jaffari","doi":"10.1145/2228360.2228396","DOIUrl":"https://doi.org/10.1145/2228360.2228396","url":null,"abstract":"Active-matrix organic light emitting diode displays are prone to significant VTH and mobility variations in low-temperature polycrystalline-silicon thin-film transistors. A low-cost characterization of these variations can lead to a practical external calibration and simulation of the display non-uniformity. This paper proposes a generic methodology based on principal component analysis, relying on the display current levels corresponding to applied characterization images. This technique results in simultaneous characterization of the VTH and mobility for the entire active matrix. Measurement results show that taking advantage of spatial correlation leads to 100 times reduction in characterization time with less than 30% relative error.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122338760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}