Small delay testing for TSVs in 3-D ICs

Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, S. Sunter, Yung-Fa Chou, D. Kwai
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引用次数: 59

Abstract

In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC. By changing the output inverter's threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault. SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test.
三维集成电路中tsv的小延迟测试
在这项工作中,我们提出了3D集成电路中硅通孔(TSV)的鲁棒小延迟测试方案。通过在可测试的振荡环结构中改变TSV的输出逆变器的阈值,我们可以近似该TSV的传播延迟,从而检测到小延迟故障。SPICE仿真结果表明,该变输出阈值(VOT)技术在检测具有电阻性开路缺陷的慢速TSV时,即使存在显著的工艺变化,也仍然有效。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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