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2008 14th IEEE International On-Line Testing Symposium最新文献

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SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation 基于系统c的改进故障表示的最小侵入性故障注入技术
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.25
R. Shafik, P. Rosinger, B. Al-Hashimi
{"title":"SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation","authors":"R. Shafik, P. Rosinger, B. Al-Hashimi","doi":"10.1109/IOLTS.2008.25","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.25","url":null,"abstract":"In this paper, we propose a new SystemC-based fault injection technique that has improved fault representation in visible and on-the-fly data and signal registers. The technique is minimum intrusive since it only requires replacing the original data or signal types to fault injection enabler types. We compare the proposed simulation technique with recently reported SystemC-based techniques and show that our technique has fast simulation speed, better fault representation, while maintaining simplicity and minimum intrusion. We demonstrate fault injection capabilities in a behavioural SystemC description of MPEG-2 decoder using proposed technique and show that up to 98.9% fault representation within data and signal registers can be achieved.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122052055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips 大规模缺陷多端口芯片的自配置和可达性度量
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.58
P. Zając, J. Collet, A. Napieralski
{"title":"Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips","authors":"P. Zając, J. Collet, A. Napieralski","doi":"10.1109/IOLTS.2008.58","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.58","url":null,"abstract":"The downsizing of transistor dimensions enabled in the future nanotechnologies will inevitably increase the number of faults in the complex ULSI chips. To maintain the production yield at acceptable level, several levels of protection mechanisms will have to be implemented to tolerate the permanent and transient faults occurring in the physical layers. In this paper, we study fault tolerance at the architectural level in multiport processor grids (MPG) through core dual diagnosis and self-configuration of communications. MPGs are considered to ensure the scalability of future hundred-core chips. We characterize defective technologies by the IOP reachability (i.e., the ability of the IOPs to contact a fraction of cores in the grid) that we study as a function of the fraction of defective cores or links. We show that almost all valid cores in the grid are accessible by all input-output ports (IOP) up to approximately 20-25% of defective cores. This property is quasi-independent of the position of the IOPs in the grid.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130858626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Dynamic Scheduling of Test Routines for Efficient Online Self-Testing of Embedded Microprocessors 嵌入式微处理器高效在线自测测试例程的动态调度
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.55
N. Bartzoudis, V. Tantsios, K. Mcdonald-Maier
{"title":"Dynamic Scheduling of Test Routines for Efficient Online Self-Testing of Embedded Microprocessors","authors":"N. Bartzoudis, V. Tantsios, K. Mcdonald-Maier","doi":"10.1109/IOLTS.2008.55","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.55","url":null,"abstract":"This paper presents a self-testing framework targeting the LEON3 embedded microprocessor with built-in test-scheduling features. The proposed design exploits existing post production test sets, designed for software-based testing of embedded microprocessors. The framework also includes a constraint-based approach of test-routine scheduling. The initial results show that the test execution time could be dynamically scaled by the test selection algorithm.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130429502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Special Session 1: Radiation Hardening Techniques 特别会议1:辐射硬化技术
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.66
N. Seifert
{"title":"Special Session 1: Radiation Hardening Techniques","authors":"N. Seifert","doi":"10.1109/IOLTS.2008.66","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.66","url":null,"abstract":"Summary form only given, as follows. While the industry does not agree on the details of soft error rate per device trends, an increase of chip-level upset rates without implementation of additional soft error mitigation features is undisputed. This session focuses on some of the latest hardening techniques introduced in the literature. Prof. Mitra of Stanford University will provide an overview of potential solutions, while Dr. N. Seifert (Intel) and Dr. P. Roche (STMicroelectronics) will be discussing measured SER data of selected hardening techniques.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126346556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A New Approach for Transient Fault Injection Using Symbolic Simulation 基于符号仿真的暂态故障注入新方法
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.59
A. Darbari, B. Al-Hashimi, P. Harrod, D. Bradley
{"title":"A New Approach for Transient Fault Injection Using Symbolic Simulation","authors":"A. Darbari, B. Al-Hashimi, P. Harrod, D. Bradley","doi":"10.1109/IOLTS.2008.59","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.59","url":null,"abstract":"One effective fault injection approach involves instrumenting the RTL in a controlled manner to incorporate fault injection, and evaluating the behaviour of the faulty RTL whilst running some benchmark programs. This approach relies on checking the effects of faults whilst the design is executing a specific binary image, and therefore the true impact of the fault is limited by the shadow of the program image. Another limitation of this approach is the use of extra hardware for fault injection which is not needed during the fault-free running of the design. The aim of this paper is to propose a new approach for transient fault injection based on symbolic simulation and model checking that circumvents the problems experienced due to application dependent fault injection and RTL modification. In this paper we present our approach and analyse the effect of transient faults on the fetch unit of a 32-bit multi-cycle RISC processor. Our approach can be applied generally to any faulty design, not necessarily a processor.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121232624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability 降低三比特误码纠错概率的新型线性SEC-DED码
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.27
Michael Richter, Klaus Oberländer, M. Gössel
{"title":"New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability","authors":"Michael Richter, Klaus Oberländer, M. Gössel","doi":"10.1109/IOLTS.2008.27","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.27","url":null,"abstract":"This paper solves the problem of minimizing triple bit error miscorrection for single-error-correcting, double-error-detecting codes (SEC-DED codes) which are used to protect all kinds of memory against errors. A lower bound for triple bit error miscorrection for the widely used class of odd-weight column codes is derived and actual codes which are very close to that theoretical bound are presented. Surprisingly, significantly better results are obtained with shortened generalized Hamming codes. An optimal (39,32)-SEC-DED code with 32 information bits and 7 control bits is determined which has the lowest risk of triple bit miscorrection of any possible linear (39,32)-code. It is shown how codes with 64 and 128 information bits with significantly lower triple bit miscorrection probability than currently used codes can be derived from that code.The new codes also feature adjacent double bit error correction capabilities (SEC-DED-DAEC codes). Employing them in a SEC-DED-DAEC checker reduces the risk of miscorrecting non-adjacent double bit errors by 27-34% compared to the best codes known.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122614849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS 先进商用CMOS技术对空间和医疗应用的兴趣日益浓厚。一种新型纳米功率和辐射硬化SRAM在130nm CMOS上的图示
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.60
P. Roche, Mark Lysinger, G. Gasiot, J. Daveau, M. Zamanian, P. Dautriche
{"title":"Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS","authors":"P. Roche, Mark Lysinger, G. Gasiot, J. Daveau, M. Zamanian, P. Dautriche","doi":"10.1109/IOLTS.2008.60","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.60","url":null,"abstract":"This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM designed in 130 nm CMOS.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131142908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reliability in Application Specific Mesh-Based NoC Architectures 应用特定网格NoC架构的可靠性
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.53
F. Refan, H. Alemzadeh, S. Safari, P. Prinetto, Z. Navabi
{"title":"Reliability in Application Specific Mesh-Based NoC Architectures","authors":"F. Refan, H. Alemzadeh, S. Safari, P. Prinetto, Z. Navabi","doi":"10.1109/IOLTS.2008.53","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.53","url":null,"abstract":"Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering from permanent switch failures via replacing them by neighboring switches. This method has hardware and power consumption overhead, but significantly improves reliability and has a very little effect on the performance of the system. We suggest a reliability analysis method based on the combinatorial reliability models and use it to evaluate our proposed fault-tolerant NoC architecture.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133287650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Communication Aware Recovery Configurations for Networks-on-Chip 片上网络的通信感知恢复配置
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.44
C. Rusu, C. Grecu, L. Anghel
{"title":"Communication Aware Recovery Configurations for Networks-on-Chip","authors":"C. Rusu, C. Grecu, L. Anghel","doi":"10.1109/IOLTS.2008.44","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.44","url":null,"abstract":"In this paper we propose a set of different configurations of failure recovery schemes, developed for network-on-chip (NoC) based systems. These configurations exploit the fact that communication in NoCs tends to be partitioned and eventually localized. The failure recovery approach is based on checkpoint and rollback and is aimed towards fast recovery from system or application level failures. The proposed recovery configurations and partitions of the NoC enhance the performance/overhead of the recovery mechanism. We analyze the effectiveness of these solutions, depending on the traffic characteristics and the expected failure rate.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"5 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130891864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Yield Improvement, Fault-Tolerance to the Rescue? 良率提高，容错拯救?
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.10
J. Vial, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel
{"title":"Yield Improvement, Fault-Tolerance to the Rescue?","authors":"J. Vial, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel","doi":"10.1109/IOLTS.2008.10","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.10","url":null,"abstract":"With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture interesting for a yield improvement purpose.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127697975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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