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2008 14th IEEE International On-Line Testing Symposium最新文献

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An Enhanced Logic BIST Architecture for Online Testing 一种用于在线测试的增强逻辑BIST体系结构
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.48
Fan Yang, S. Chakravarty, Narendra Devta-Prasanna, S. Reddy, I. Pomeranz
{"title":"An Enhanced Logic BIST Architecture for Online Testing","authors":"Fan Yang, S. Chakravarty, Narendra Devta-Prasanna, S. Reddy, I. Pomeranz","doi":"10.1109/IOLTS.2008.48","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.48","url":null,"abstract":"The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture to detect such defects is proposed. Unlike other sequences, like checking experiments, the enhancements are simple and independent of the circuit under test.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125814137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Totally Fault Tolerant RNS Based FIR Filters 完全容错的基于RNS的FIR滤波器
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.14
S. Pontarelli, G. Cardarilli, M. Re, A. Salsano
{"title":"Totally Fault Tolerant RNS Based FIR Filters","authors":"S. Pontarelli, G. Cardarilli, M. Re, A. Salsano","doi":"10.1109/IOLTS.2008.14","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.14","url":null,"abstract":"In this paper, the design of a finite impulse response (FIR) filter with fault tolerant capabilities based on the residue number system is analyzed. Differently from other approaches that use RNS, the filter implementation is fault tolerant not only with respect to a fault inside the RNS moduli, but also in the reverse converter. An architecture allowing fault masking in the overall RNS FIR filter is presented. It avoids the use of a trivial triple modular redundancy (TMR) to protect the blocks that performs the final stages of the RNS based FIR computation.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125900950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 107
On-Line Testing of Lab-on-Chip Using Digital Microfluidic Compactors 基于数字微流控压实机的芯片实验室在线测试
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.45
Yang Zhao, K. Chakrabarty
{"title":"On-Line Testing of Lab-on-Chip Using Digital Microfluidic Compactors","authors":"Yang Zhao, K. Chakrabarty","doi":"10.1109/IOLTS.2008.45","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.45","url":null,"abstract":"Dependability is an important system attribute for microfluidic lab-on-chip devices. On-line testing offers a promising method for detecting defects, fluidic abnormalities, and bioassay malfunctions during chip operation. However, previous techniques for reading test outcomes and analyzing pulse sequences are cumbersome, sensitive to the calibration of capacitive sensors, and error-prone. We present a built-in self-test (BIST) method for on-line testing of digital microfluidic lab-on-chip. This method utilizes microfluidic compactors based on droplet-based AND gates, which are implemented using digital microfluidics. Dynamic reconfiguration of these compactors ensures low area overhead and it allows BIST to be interleaved with bioassays in functional mode.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123005460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
False Error Study of On-line Soft Error Detection Mechanisms 在线软错误检测机制的虚假错误研究
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.29
M. K. Reddy, B. Amrutur, R. Parekhji
{"title":"False Error Study of On-line Soft Error Detection Mechanisms","authors":"M. K. Reddy, B. Amrutur, R. Parekhji","doi":"10.1109/IOLTS.2008.29","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.29","url":null,"abstract":"With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double sampling checker (used in Razor), is the simplest and most area and power efficient, but suffers from very high false detection rates of 1.15 times the actual error rates. We also find that the alternate approaches of triple sampling and integrate and sample method (I&S) can be designed to have zero false detection rates, but at an increased area, power and implementation complexity. The triple sampling method has about 1.74 times the area and twice the power as compared to the Double Sampling method and also needs a complex clock generation scheme. The I&S method needs about 16% more power with 0.58 times the area as double sampling, but comes with more stringent implementation constraints as it requires detection of small voltage swings.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128730645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
SRAM Cell Design Protected from SEU Upsets SRAM单元设计保护了SEU干扰
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.49
Y. Shiyanovskii, F. Wolff, C. Papachristou
{"title":"SRAM Cell Design Protected from SEU Upsets","authors":"Y. Shiyanovskii, F. Wolff, C. Papachristou","doi":"10.1109/IOLTS.2008.49","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.49","url":null,"abstract":"There have been many solutions to create a soft error immune SRAM cell. These solutions can be broken down into three categories: a) hardening, b) recovery, c) protection. Hardening techniques insert circuitry in an SRAM cell possibly duplicating the number of transistors. Recovery techniques insert current monitors in SRAMs to detect SEUs and they employ error correcting codes or redundancy to mitigate these effects. These techniques do not scale very well. Protection methods use capacitors in SRAM cells to absorb the excessive charge. Although they provide sufficient protection, they affect adversely the write time.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130351605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection 联机单误校正和双误检测的位并行伽罗瓦场乘法器设计技术
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.34
J. Mathew, A. Jabir, D. Pradhan
{"title":"Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection","authors":"J. Mathew, A. Jabir, D. Pradhan","doi":"10.1109/IOLTS.2008.34","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.34","url":null,"abstract":"Error correction is an effective way to mitigate fault attacks in cryptographic hardware. It is also an effective solution to soft errors in deep sub-micron technologies. To this end, we present a systematic method for designing single error correcting (SEC) and double error detecting (DED) finite field (Galoisfield) multipliers over GF(2m). The detection and correction are done on-line. We use multiple Parity Predictions (PPs) to correct single errors based on the Hamming principles. Specifically, a structural approach is first presented. The predicted parities are derived from the input operands. Further, a hybrid approach is presented where the multipliers and PP circuits are synthesized, and the decoding and correction circuits are structurally combined to form the complete error correcting designs. Our technique, when compared with existing techniques, gives better performance. We show that our SEC multipliers over GF(2m) require about 100% extra hardware, whereas with the traditional SEC techniques, such as the triple-modular redundancy (TMR), this figure is more than 200%.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131385568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
SDRAM Architecture & Single Event Effects Revealed with Laser 用激光揭示SDRAM结构和单事件效应
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.40
A. Bougerol, F. Miller, N. Buard
{"title":"SDRAM Architecture & Single Event Effects Revealed with Laser","authors":"A. Bougerol, F. Miller, N. Buard","doi":"10.1109/IOLTS.2008.40","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.40","url":null,"abstract":"This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements, which is essential to know the number of bits that can be involved in a MBU. Finally at device level, laser is used to trigger different categories of Single Event Effects, and specific events like SEFIs and SELs can be precisely located. All these information allow to get an estimation of heavy ion saturated cross section for each events, which is usually difficult to obtain with particle accelerators.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132368526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Directed Random SBST Generation for On-Line Testing of Pipelined Processors 面向流水线处理器在线测试的定向随机SBST生成
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.18
A. Merentitis, G. Theodorou, Mihalis Giorgaras, N. Kranitis
{"title":"Directed Random SBST Generation for On-Line Testing of Pipelined Processors","authors":"A. Merentitis, G. Theodorou, Mihalis Giorgaras, N. Kranitis","doi":"10.1109/IOLTS.2008.18","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.18","url":null,"abstract":"Software-based self-test (SBST) has emerged as an effective strategy for non-concurrent on-line testing of processors integrated in embedded system applications. It offers the potential for on-line testing without any hardware overhead. However, test generation is usually based in a semi-automated approach and gate-level information is required for effective test program generation.In this paper we present a methodology for converting processor validation tests in order to perform automated directed random SBST routine generation, based on templates that are developed utilizing a combination of functional and high-level structural pattern generation approaches. The methodology is applied on the OpenRISC 1200 processor, easily achieving test coverage of 86.43%, using only low-effort gate-level independent code generation.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133280761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Propagation of Transients Along Sensitizable Paths 瞬态沿敏化路径的传播
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.46
S. Gangadhar, Michael N. Skoufis, S. Tragoudas
{"title":"Propagation of Transients Along Sensitizable Paths","authors":"S. Gangadhar, Michael N. Skoufis, S. Tragoudas","doi":"10.1109/IOLTS.2008.46","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.46","url":null,"abstract":"Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation under estimates the number of sensitizable paths per circuit. This leads to inconclusive and overly optimistic results when a worst-case analysis is required. In this paper, we present a zero-suppressed binary decision diagram (ZBDD) centered framework, for a complete consideration of all potentially sensitizable paths per circuit. The proposed method is validated in logic paths by evaluating worst-case transient-wave electrical characteristics, such as maximum duration and corresponding amplitude at the circuit outputs.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117330453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
On-Line Failure Detection and Confinement in Caches 缓存中的在线故障检测和限制
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.15
J. Abella, P. Chaparro, X. Vera, J. Carretero, Antonio González
{"title":"On-Line Failure Detection and Confinement in Caches","authors":"J. Abella, P. Chaparro, X. Vera, J. Carretero, Antonio González","doi":"10.1109/IOLTS.2008.15","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.15","url":null,"abstract":"Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need for continuous on-line testing techniques to cope with hard errors in the field. Similarly, those techniques are needed for detecting soft errors in logic, whose error rate is expected to raise in future technologies. Cache memories, which occupy most of the area of the chip, are typically protected with parity or ECC, but most of the wires as well as some combinational blocks remain unprotected against both soft and hard errors. This paper presents a set of techniques to detect and confine hard and soft errors in cache memories in combination with parity/ECC at very low cost. By means of hard signatures in data rows and error tracking, faults can be detected, classified properly and confined for hardware reconfiguration.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116296601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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