Directed Random SBST Generation for On-Line Testing of Pipelined Processors

Abstract

Software-based self-test (SBST) has emerged as an effective strategy for non-concurrent on-line testing of processors integrated in embedded system applications. It offers the potential for on-line testing without any hardware overhead. However, test generation is usually based in a semi-automated approach and gate-level information is required for effective test program generation.In this paper we present a methodology for converting processor validation tests in order to perform automated directed random SBST routine generation, based on templates that are developed utilizing a combination of functional and high-level structural pattern generation approaches. The methodology is applied on the OpenRISC 1200 processor, easily achieving test coverage of 86.43%, using only low-effort gate-level independent code generation.