J. Vial, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel
{"title":"良率提高，容错拯救?","authors":"J. Vial, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel","doi":"10.1109/IOLTS.2008.10","DOIUrl":null,"url":null,"abstract":"With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture interesting for a yield improvement purpose.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Yield Improvement, Fault-Tolerance to the Rescue?\",\"authors\":\"J. Vial, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel\",\"doi\":\"10.1109/IOLTS.2008.10\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture interesting for a yield improvement purpose.\",\"PeriodicalId\":261786,\"journal\":{\"name\":\"2008 14th IEEE International On-Line Testing Symposium\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 14th IEEE International On-Line Testing Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IOLTS.2008.10\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 14th IEEE International On-Line Testing Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IOLTS.2008.10","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture interesting for a yield improvement purpose.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
