{"title":"特别会议1:辐射硬化技术","authors":"N. Seifert","doi":"10.1109/IOLTS.2008.66","DOIUrl":null,"url":null,"abstract":"Summary form only given, as follows. While the industry does not agree on the details of soft error rate per device trends, an increase of chip-level upset rates without implementation of additional soft error mitigation features is undisputed. This session focuses on some of the latest hardening techniques introduced in the literature. Prof. Mitra of Stanford University will provide an overview of potential solutions, while Dr. N. Seifert (Intel) and Dr. P. Roche (STMicroelectronics) will be discussing measured SER data of selected hardening techniques.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Special Session 1: Radiation Hardening Techniques\",\"authors\":\"N. Seifert\",\"doi\":\"10.1109/IOLTS.2008.66\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given, as follows. While the industry does not agree on the details of soft error rate per device trends, an increase of chip-level upset rates without implementation of additional soft error mitigation features is undisputed. This session focuses on some of the latest hardening techniques introduced in the literature. Prof. Mitra of Stanford University will provide an overview of potential solutions, while Dr. N. Seifert (Intel) and Dr. P. Roche (STMicroelectronics) will be discussing measured SER data of selected hardening techniques.\",\"PeriodicalId\":261786,\"journal\":{\"name\":\"2008 14th IEEE International On-Line Testing Symposium\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 14th IEEE International On-Line Testing Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IOLTS.2008.66\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 14th IEEE International On-Line Testing Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IOLTS.2008.66","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Summary form only given, as follows. While the industry does not agree on the details of soft error rate per device trends, an increase of chip-level upset rates without implementation of additional soft error mitigation features is undisputed. This session focuses on some of the latest hardening techniques introduced in the literature. Prof. Mitra of Stanford University will provide an overview of potential solutions, while Dr. N. Seifert (Intel) and Dr. P. Roche (STMicroelectronics) will be discussing measured SER data of selected hardening techniques.