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A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing 一种新的基于ga的高阶合成技术增强RT-Level并发测试
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.43
Naghmeh Karimi, Soheil Aminzadeh, S. Safari, Z. Navabi
{"title":"A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing","authors":"Naghmeh Karimi, Soheil Aminzadeh, S. Safari, Z. Navabi","doi":"10.1109/IOLTS.2008.43","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.43","url":null,"abstract":"This paper presents an efficient high-level synthesis (HLS) approach to improve RT-level concurrent testing. The proposed method used for both fault detection and fault location. At first the available resources are used in their dead intervals to test active resources for fault detection, and then some changes are applied to the RT-level controller to locate the faults. The fault detection step is based on a genetic algorithm (GA) search technique. This genetic algorithm is applied to the design after high level synthesis process to explore the test map. The proposed method has been evaluated based on dependability enhancement and area/latency overhead imposed to different benchmarks after applying our algorithm. The dependability has been considered in terms of fault coverage. The experimental result shows that applying our algorithm, the associated area overhead and performance penalty are negligible while the online fault coverage improvement is considerable.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123053159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD 利用SPFD最小化逻辑电路中的潜在暂态误差和SER
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.16
S. Almukhaizim, Y. Makris, Yu-Shen Yang, A. Veneris
{"title":"On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD","authors":"S. Almukhaizim, Y. Makris, Yu-Shen Yang, A. Veneris","doi":"10.1109/IOLTS.2008.16","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.16","url":null,"abstract":"Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises superiority in exploring the flexibility offered by a design over all previous representation methods. In this work, we illustrate how the SPFD of a particular wire reveals information regarding the number of potential transient errors that may occur on that wire and may affect the output of the circuit. Using an SPFD-based rewiring method, we then demonstrate how to evolve a logic circuit in order to minimize the total number of potential transient errors in the circuit and, consequently, reduce its Soft Error Rate (SER) while controlling the effect on the rest of the design parameters, such as area, power, delay, and testability. Experimental results on ISCAS'89 and ITC'99 benchmark circuits indicate that the SER can be reduced at no additional overhead to any of the design parameters.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116742334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Fault-Tolerant Attitude Determination System Based on COTS Devices 基于COTS器件的容错姿态确定系统
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.20
R. O. Duarte, L. Martins-Filho, Guilherme F. T. Knop, R. S. Prado
{"title":"A Fault-Tolerant Attitude Determination System Based on COTS Devices","authors":"R. O. Duarte, L. Martins-Filho, Guilherme F. T. Knop, R. S. Prado","doi":"10.1109/IOLTS.2008.20","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.20","url":null,"abstract":"In this paper we present a low cost fault-tolerant attitude determination system to a scientific satellite using COTS devices. We related our experience in developing the attitude determination system, where we combine proven fault tolerance techniques to protect the whole system composed only by COTS from the effects produced by transient faults. We detailed the failure cases and the detection, reconfiguration and recovery schemes that assure the fault-tolerant condition. A testbed system was used to inject faults, evaluate the recovery capability of the fault-tolerant system and validate the solution proposed.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127076385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A BISR Architecture for Embedded Memories 嵌入式存储器的BISR体系结构
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.21
K. Pekmestzi, N. Axelos, I. Sideris, N. Moschopoulos
{"title":"A BISR Architecture for Embedded Memories","authors":"K. Pekmestzi, N. Axelos, I. Sideris, N. Moschopoulos","doi":"10.1109/IOLTS.2008.21","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.21","url":null,"abstract":"In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities. On a 4 Mbit memory and an average number of 1024 memory defects per IC, a repair ratio of 100% and over 90% require less than 2% and 1% memory overhead respectively.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124160506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Variation of SRAM Alpha-Induced Soft Error Rate with Technology Node SRAM α诱发软错误率随技术节点的变化
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.38
Damien Leroy, R. Gaillard, E. Schäfer, Cyrille Beltrando, S. Wen, R. Wong
{"title":"Variation of SRAM Alpha-Induced Soft Error Rate with Technology Node","authors":"Damien Leroy, R. Gaillard, E. Schäfer, Cyrille Beltrando, S. Wen, R. Wong","doi":"10.1109/IOLTS.2008.38","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.38","url":null,"abstract":"This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122059060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Soft Error Protection Techniques 软错误保护技术
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.64
S. Mitra
{"title":"Soft Error Protection Techniques","authors":"S. Mitra","doi":"10.1109/IOLTS.2008.64","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.64","url":null,"abstract":"","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133985997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force? 特别会议2:基于软件的SER特性的基准和标准化:迈向IEEE工作组?
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.67
M. Nicolaidis
{"title":"Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force?","authors":"M. Nicolaidis","doi":"10.1109/IOLTS.2008.67","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.67","url":null,"abstract":"The present invention provides novel ophthalmic drug delivery formulation which comprises a mixture of Carbopol and Pluronic. Carbopol is a trademark of B.F. Goodrich Company's high molecular weight carboxy vinyl polymers (MW above 1,000,000). Pluronic belongs to a class of block copolymers containing polyoxyethylene and polyoxypropylene. The preferred weight percentages of Carbopol and Pluronic in the ophthalmic drug delivery formulation are 0.3% of Carbopol and 14% of Pluronic. The ocular bioavailability is greatly enhanced by the use of the ophthalmic drug delivery formulation of the present invention.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134266754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement 在H-Tree RAM结构中嵌入电流监测以提高多单股电容错性和可靠性
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.36
C. Argyrides, F. Vargas, M. Moraes, D. Pradhan
{"title":"Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement","authors":"C. Argyrides, F. Vargas, M. Moraes, D. Pradhan","doi":"10.1109/IOLTS.2008.36","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.36","url":null,"abstract":"In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking is performed on an H-tree SRAM in different ways. We demonstrate the assertions of the proposed technique by performing a reliability analysis while combining current monitoring with a single-parity bit or Hamming codes per RAM word to perform single or multiple error correction.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115286496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Low-Cost Accumulator-Based Test Pattern Generation Architecture 基于累加器的低成本测试模式生成体系结构
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.54
D. Magos, I. Voyiatzis, S. Tarnick
{"title":"A Low-Cost Accumulator-Based Test Pattern Generation Architecture","authors":"D. Magos, I. Voyiatzis, S. Tarnick","doi":"10.1109/IOLTS.2008.54","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.54","url":null,"abstract":"A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding approaches for accumulator-based test generation.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126589972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Deterministic Built-in TPG with Segmented FSMs 带有分段fsm的确定性内置TPG
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.37
S. Sudireddy, Jayawant Kakade, D. Kagaris
{"title":"Deterministic Built-in TPG with Segmented FSMs","authors":"S. Sudireddy, Jayawant Kakade, D. Kagaris","doi":"10.1109/IOLTS.2008.37","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.37","url":null,"abstract":"We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM) with log2 ri flip-flops. As all FSMs run through their states, all patterns of T are generated in time R. Experimental results show that with appropriate filling of the don't cares to reduce the number of representatives in each segment, and with the use of standard sequential synthesis tools, the scheme can offer low hardware overhead as well as low number R of test cycles.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127732454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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