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2008 14th IEEE International On-Line Testing Symposium最新文献

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Soft-Error Vulnerability of Sub-100-nm Flip-Flops 100nm以下触发器的软错误漏洞
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.12
T. Heijmen
{"title":"Soft-Error Vulnerability of Sub-100-nm Flip-Flops","authors":"T. Heijmen","doi":"10.1109/IOLTS.2008.12","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.12","url":null,"abstract":"The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate estimation of the contribution of flip-flops to the SER of an IC. The method is applicable to frequencies well below 1 GHz. The approach is based on a set of expressions for the timing vulnerability factor (TVF) of the master and slave latches of the flip-flop. With this approach it is possible to make an accurate estimation of the flip-flop SER parameters.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115803686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A Modular Memory BIST for Optimized Memory Repair 一种用于优化内存修复的模块化内存BIST
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.30
P. Öhler, A. Bosio, G. D. Natale, S. Hellebrand
{"title":"A Modular Memory BIST for Optimized Memory Repair","authors":"P. Öhler, A. Bosio, G. D. Natale, S. Hellebrand","doi":"10.1109/IOLTS.2008.30","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.30","url":null,"abstract":"An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Most of the existing built-in self-repair solutions reuse IP-Cores for BIST without modifications. However, this prevents an optimized test and repair interaction. In this paper, the concept of modular BIST for memories is introduced, which supports a more efficient interleaving of test and repair and can be achieved with only small modifications in the BIST control.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"107 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130469634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring 基于片上监测的ssn诱发逻辑错误检测研究
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.19
F. Azaïs, Laurent Larguier, Y. Bertrand, M. Renovell
{"title":"On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring","authors":"F. Azaïs, Laurent Larguier, Y. Bertrand, M. Renovell","doi":"10.1109/IOLTS.2008.19","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.19","url":null,"abstract":"Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the variations of power/ground lines at the interface between noncoherent logic blocks in order to warn that a logic error is likely to occur. This information can then be used for any scheme that takes corrective actions.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124938984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits 利用参数电源和/或温度变化来提高数字电路的容错性
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.51
J. Semião, J. Freijedo, J. Rodríguez-Andina, F. Vargas, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira
{"title":"Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits","authors":"J. Semião, J. Freijedo, J. Rodríguez-Andina, F. Vargas, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira","doi":"10.1109/IOLTS.2008.51","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.51","url":null,"abstract":"The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology is reviewed, highlighting its characteristics and limitations. The underlying principle is to introduce on-line additional tolerance, by dynamically controlling the time of the clock edge trigger driving specific memory cells. Second, it is shown that the proposed methodology is still useful in the presence of process variations. Third, discussion and preliminary results on the automatic selection (at gate level) of critical FF for which DDB insertion should take place are presented. Finally, it is shown that parametric delay tolerance insertion does not necessarily reduce delay fault detection, as multi-vdd or multi-frequency self-test can be used to recover detection capability.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127255100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs 在45nm技术lsi中使用低通滤波器抑制单事件瞬变
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.28
T. Uemura, R. Tanabe, Y. Tosaka, S. Satoh
{"title":"Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs","authors":"T. Uemura, R. Tanabe, Y. Tosaka, S. Satoh","doi":"10.1109/IOLTS.2008.28","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.28","url":null,"abstract":"In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We proposed a flip-flop of SET-SEU-RHBD. This flip-flop has LPF using a C-element with dual transmission and applies an MNL technique only on the master latch. This flip-flop is designed with 45-nm technology and a 16-grid height. Mitigation efficiencies of the flip-flop are estimated by accelerated experiments and simulations. The flip-flop can protect 90% of SEU and 52 ps SET pulse with low penalties.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117179537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A Systematical Method of Quantifying SEU FIT 定量SEU FIT的系统方法
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.62
Shi-Jie Wen, D. Alexandrescu, R. Perez
{"title":"A Systematical Method of Quantifying SEU FIT","authors":"Shi-Jie Wen, D. Alexandrescu, R. Perez","doi":"10.1109/IOLTS.2008.62","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.62","url":null,"abstract":"We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly demanding reliability requirements.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122257562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Integrating Scan Design and Soft Error Correction in Low-Power Applications 集成扫描设计和软错误校正在低功耗应用
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.31
M. Imhof, H. Wunderlich, Christian G. Zoellin
{"title":"Integrating Scan Design and Soft Error Correction in Low-Power Applications","authors":"M. Imhof, H. Wunderlich, Christian G. Zoellin","doi":"10.1109/IOLTS.2008.31","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.31","url":null,"abstract":"Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. Often latches are clock gated and have to retain their states during longer periods. Moreover, miniaturization has led to elevated susceptibility of the memory elements and further increases the need for protection. This paper presents a fault-tolerant register latch organization that is able to detect single-bit errors while it is clock gated. With active clock, single and multiple errors are detected. The registers can be efficiently integrated similar to the scan design flow, and error detecting or locating information can be collected at module level. The resulting structure can be efficiently reused for offline and general online testing.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129227052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Budget-Dependent Control-Flow Error Detection 预算相关的控制流错误检测
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.52
Ramtilak Vemu, J. Abraham
{"title":"Budget-Dependent Control-Flow Error Detection","authors":"Ramtilak Vemu, J. Abraham","doi":"10.1109/IOLTS.2008.52","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.52","url":null,"abstract":"The problem of detection of control flow errors in software has been studied extensively in literature and many detection techniques have been proposed. These techniques typically have high memory and performance overheads and hence are unusable for real-time embedded systems which have tight memory and performance budgets. This paper presents two algorithms by which the overheads associated with any detection technique can be lowered by trading off fault coverage. These algorithms are generic and can be applied to any detection technique. They can be applied either individually or cumulatively. The algorithms are validated on a previously proposed detection technique using SPEC benchmark programs. Fault injection experiments suggest that massive savings in overheads can be achieved using the algorithms with just a minor drop off in fault coverage.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117353204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Fault Tolerant Reversible Finite Field Arithmetic Circuits 容错可逆有限域算术电路
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.35
J. Mathew, Jawar Singh, Anas Abu Taleb, D. Pradhan
{"title":"Fault Tolerant Reversible Finite Field Arithmetic Circuits","authors":"J. Mathew, Jawar Singh, Anas Abu Taleb, D. Pradhan","doi":"10.1109/IOLTS.2008.35","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.35","url":null,"abstract":"In this paper, we present a systematic method for the designing fault tolerant reversible arithmetic circuits for finite field or Galois fields of the form GF(2m). To tackle the problem of errors in computation, we propose error detection and correction using multiple parity prediction technique based on low density parity check (LDPC) code. For error detection and correction, we need additional garbage outputs. Our technique, when compared with traditional fault tolerant approach gives better implementation cost.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130489160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Developing Fault Injection Environment for Complex Experiments 复杂实验故障注入环境的开发
2008 14th IEEE International On-Line Testing Symposium Pub Date : 2008-07-07 DOI: 10.1109/IOLTS.2008.13
P. Gawkowski, J. Sosnowski
{"title":"Developing Fault Injection Environment for Complex Experiments","authors":"P. Gawkowski, J. Sosnowski","doi":"10.1109/IOLTS.2008.13","DOIUrl":"https://doi.org/10.1109/IOLTS.2008.13","url":null,"abstract":"The paper addresses the problem of creating a comprehensive fault injection environment, which integrates and improves various simulation and supplementary functions. This is illustrated with experimental results.","PeriodicalId":261786,"journal":{"name":"2008 14th IEEE International On-Line Testing Symposium","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132076332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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