Deterministic Built-in TPG with Segmented FSMs

Abstract

We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM) with log2 ri flip-flops. As all FSMs run through their states, all patterns of T are generated in time R. Experimental results show that with appropriate filling of the don't cares to reduce the number of representatives in each segment, and with the use of standard sequential synthesis tools, the scheme can offer low hardware overhead as well as low number R of test cycles.