S. Ramamurthy, N. Tam, B. Ramachandran, T. Dixit, Eun-Ha Kim, H. Forstner
{"title":"Spike anneal for NiSi formation","authors":"S. Ramamurthy, N. Tam, B. Ramachandran, T. Dixit, Eun-Ha Kim, H. Forstner","doi":"10.1109/RTP.2004.1441947","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441947","url":null,"abstract":"The design of wafer processing equipment needs to continuously evolve and respond to the challenges of the future. In this article, we present the evolution of rapid thermal processing (RTP) in the transistor manufacturing environment with emphasis on production-worthy performance over a temperature regime that addresses the sub-400degC processing requirements. Temperature and thermal budget control is increasingly critical for contact material processing for sub-65 nm nodes. We present low temperature spike anneal as an application to address thermal budget challenges and demonstrate the extendibility of lamp-based RTP to low temperature processes","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115621167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Leveraging a low pressure thermal module to meet the challenges of advanced device manufacturing","authors":"B. Peuse, M. Pfarr, P. Timans, Y. Hu","doi":"10.1109/RTP.2004.1441938","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441938","url":null,"abstract":"Fulfilling the needs of advanced semiconductor device manufacturing presents continued challenges to the developers and manufacturers of capital equipment. More than twenty years of RTP equipment evolution and development has resulted in the availability of a select few technologies that are capable of delivering the demanding performance required to manufacturer today's advanced semiconductor devices. This paper describes the development and characterization of a new low pressure RTP process module that was developed to fulfil some specific needs. With the use of proven existing thermal processing technology, the design, development, characterization and qualification of this module for device manufacturing was done in a very short period of time","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126776036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Infusion processing solutions for USJ and localized strained-Si using gas cluster ion beams","authors":"J. Hautala, J. Borland","doi":"10.1109/RTP.2004.1441709","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441709","url":null,"abstract":"Infusion processing using gas cluster ion beam (GCIB) technology provides several new capabilities in the areas of ultra shallow junction formation and localized or blanket SiGe formation resulting in strained-Si. This room temperature process requires only solid phase epitaxy (SPE) anneals (<700degC) for diffusionless activation and high quality SiGe or Ge formation. Initial tests indicate all standard annealing methods are compatible with the process. For the formation of ultra shallow junctions, there are four enabling aspects to this new technology: 1) no channeling is observed, so a pre-amorphizing implant (PAI) is not required for Xj<10 nm; 2) a box-like profile of the dopant can be engineered; 3) no end of range (EOR) damage is observed when Ge is included in the cluster. This creates a self-amorphizing infusion doping step that potentially advances the use of the various diffusionless activation methods since there is no issue with junction leakage; 4) by increasing the amount of Ge incorporated in the cluster and as a result into the Si surface, the boron solid solubility (Bss) can be increased, thereby lowering the Rs and Rext for the source drain extension structures. When higher infusion doses of GeH4 and/or SiH4 containing clusters are used, dose controlled deposition (DCD) occurs. The DCD infusion process appears to be insensitive to surface impurities such as native oxide due to the highly localized transient thermal spike (TTS). This produces a 100% amorphous layer with no post deposition interfacial layer enabling complete single crystal epitaxial regrowth of the Ge or SiGe at temperatures down to 550degC. Since this is a room temperature process, the localized infusion and deposition are compatible with photoresist patterning","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115129060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Yoo, T. Fukada, T. Murakami, K. Kang, J. Foggiato
{"title":"Design of a hot wall-based low temperature annealing system and its process applications","authors":"W. Yoo, T. Fukada, T. Murakami, K. Kang, J. Foggiato","doi":"10.1109/RTP.2004.1441941","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441941","url":null,"abstract":"A hot wall-based low temperature annealing system using resistively heated, stacked hot plates was designed and tested for low temperature (100~500degC) annealing applications for 200 mm and 300 mm wafers. The system is designed to process five wafers simultaneously for productivity enhancement purposes. Thermal properties of the system and wafer temperature profiles during low temperature annealing in stacked hot plates were characterized as a function of hot plate temperature. The stacked hot plate configuration with proper gap between wafer and surrounding hot plates makes convection heat transfer predominant and provides uniform and repeatable process results in the low temperature region. Process uniformity and repeatability of NiSi formation, Cu annealing, Al sintering, spin-on-dielectrics (SOD) anneal were confirmed in the temperature range of 100~500degC","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123170406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sug-Woo Jung, Hyun-Su Kim, E. Jung, S. Cheong, J. Yun, K. Roh, J. Ku, G. Choi, Sung-tae Kim, U. Chung, J. Moon, B. Ryu
{"title":"Effect of a noble annealing system on nickel silicide formation","authors":"Sug-Woo Jung, Hyun-Su Kim, E. Jung, S. Cheong, J. Yun, K. Roh, J. Ku, G. Choi, Sung-tae Kim, U. Chung, J. Moon, B. Ryu","doi":"10.1109/RTP.2004.1441946","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441946","url":null,"abstract":"We have investigated the formation of NiSi dependence on three types of annealing systems: annealing systems-I, -II, and -III. The annealing system-I transfers heat by radiation from tungsten halogen lamps in a N2 atmosphere to the wafer and the annealing system-II by conduction from a heated hot plate in vacuum to the wafer. On the other hand, annealing system-III uses a combination of convective and gas phase conductive heat transfer in a N2 atmosphere for wafer heating. Smooth surface and interface morphologies and good electrical properties were obtained for NiSi layers formed using annealing system-III. The wafer heat transfer mechanism from the heat source to wafer is shown to influence the morphological and electrical properties of NiSi","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"109 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131943588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Alignment mark shift due to thermal non-uniformity: what is moving?","authors":"B. Lojek, M. Whiteman, K. Starzinski","doi":"10.1109/RTP.2004.1441955","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441955","url":null,"abstract":"The ITRS working group has identified mask alignment and overlay control as a technology roadblock with no known solutions beyond the 65 nm node. Mechanical stress induced by thermal processing critically influences the distortion and warpage of wafers. This paper investigates the wafer distortion between source/drain and contact masking steps. In the experimental part of this work we demonstrated that certain temperature non-uniformity patterns with uniformity less than 1% generate bigger warpage of processed wafer than a less uniform pattern with a higher non-uniformity","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132343945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"NiSi contact formation - process integration advantages with partial Ni conversion","authors":"K. Funk, X. Pagès, V. Kuznetsov, E. Granneman","doi":"10.1109/RTP.2004.1441942","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441942","url":null,"abstract":"Investigations for next generation contacts of silicon and SiGe devices show that a 2-step nickel salicidation process is favorable over a single step NiSi and over CoSi2 in every respect and can be introduced easily in existing and advanced not fully depleted CMOS flows once the post silicidation thermal treatments can be kept below 700degC. Partial conversion for the deposited Ni layer to Ni2 Si in a first RTP1 step at temperatures as low as 250degC avoids the reverse linewidth effect and enables superior uniformities over complete conversion. A second RTP2 step at typically 450degC is used to form low resistivity NiSi with less silicon consumption and lower contact resistivities than today's CoSi2 contacts. Challenging integration issue are peripheral leakage currents, that are likely to be related to undesired low temperature pyramidal NiSi2 formation and spiking","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"435 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116010777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Post BF/sub 2//sup +/ implant annealing using single wafer rapid thermal furnace","authors":"T. Fukada, W. Yoo","doi":"10.1109/RTP.2004.1441949","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441949","url":null,"abstract":"49BF2 + implanted wafers were annealed in the temperature range of 900degC and 1100degC using a single wafer rapid thermal furnace for 30 sec to 1800 sec under N2 ambient at atmospheric pressure. Sheet resistance and its uniformity were measured. Boron and fluorine depth profiles at different annealing temperatures and times were analyzed using secondary ion mass spectroscopy (SIMS). The minimum sheet resistance of 67.46 Omega/sq. with a uniformity of 0.57% (1sigma) was achieved at 1000degC for 90 s annealing time. Good uniformity with good productivity was attained with the sheet resistance decreasing as annealing temperature and time increased. Boron moved toward the silicon surface during annealing as was observed through SIMS analysis and fluorine desorption was enhanced with increasing annealing temperature and time. The electrically activated dopant concentration was calculated by evaluation of the sheet resistance and the junction depth estimated from SIMS depth profile. The concentration was on the order of 1020 atoms/cm3 regardless of annealing temperature and was closer to the solid solubility of boron in silicon as reported in the past. It is recommended that the appropriate dosage and implant energy should be selected in order to prevent inactive dopant existence and unnecessary diffusion due to an unnecessarily high gradient of dopant concentration","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122212400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wafer temperature non-uniformity due to volumetric absorption of radiation","authors":"B. Lojek","doi":"10.1109/RTP.2004.1441966","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441966","url":null,"abstract":"Until recently, the semiconductor production wafer processed in a rapid thermal processing system was considered to be an opaque material where all of the incident irradiation is absorbed by the surface and volume absorption has no significance. Such an approach cannot explain several experimentally observed effects such as the different emissivity of doped and un-doped regions, difference in temperatures between die and its boundary, etc. This paper describes a method of solution of heat transfer in semitransparent medium. An example illustrates the impact of semitransparency on the wafer temperature distribution","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124130224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling and experimental results for an RTP light-pipe radiation thermometer calibration testbed","authors":"K. Ball, J. Howell","doi":"10.1109/RTP.2004.1441961","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441961","url":null,"abstract":"A thermometry testbed designed for the testing, analysis, and calibration of light pipe thermometers and thermocouple-instrumented silicon wafers used in RTP tools has been constructed, and comparison of measured wafer temperature distributions on the instrumented wafers with light-pipe radiation thermometer measurements have been carried out. The test chamber has been modeled using detailed Monte Carlo simulation including measured specular/diffuse surface properties, and predictions of the model have been compared with measured results and are presented. The chamber is presently being modified to test advanced temperature measurement techniques, which are also described","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129419821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}