12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.最新文献

{"title":"RTP application and technology options for the sub-45 nm nodes","authors":"R. MacKnight, P. Timans, S. Tay, Z. Nényei","doi":"10.1109/RTP.2004.1441707","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441707","url":null,"abstract":"As device dimensions have reduced to nanometer length scales, rapid thermal processing (RTP) has emerged as the key approach for providing the low thermal budget and ultra-pure process conditions that are essential in advanced fabrication schemes. As further progress in electronic technology becomes increasingly dependent on success in rapid development cycles that include both materials innovations and changes in CMOS device architecture, RTP will play a major role in the story. RTP will contribute in gate-stack engineering, oxidation processes, ultra-shallow junctions, silicide formation, low-k dielectric annealing and in fundamental improvement of thin film properties. As device dimensions are controlled at the atomic scale, the concepts of thermal budget reduction will continue to drive the technology, with reductions in both process times and process temperatures combined with control of a very high purity process gas ambient. The thermal and ambient flexibility of RTP will become even more important as processes are developed and optimized for new gate dielectrics, high-mobility channel designs and metal gates combined with device architecture changes such as multiple-gate transistor designs. As the transistor channel length scales towards the ultimate limit imposed by atomic-scale fluctuations and quantum effects, the need for minimization of parasitic resistance and capacitance will become increasingly dominant in device performance. Here, the most critical requirements are to increase the concentrations of electrically active dopants without inducing excessive diffusion and to reduce contact resistances. These challenges will be met through innovation in RTP that addresses opportunities in materials engineering and in thermal cycle design. Further advances in silicon device technology will ultimately be limited by manufacturing costs. Pressure for manufacturing cycle-time reductions will mean that single-wafer processing technologies, including RTP, will continue to displace batch processing approaches. The final blow for the batch furnace will come from the transition to even larger wafer sizes, where the planar heating geometry inherent in RTP provides a natural fit to the wafer","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126032909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RTP uniformity improvement through simulation","authors":"C. Tanasa, J. Ranish, A. Hunter, S. Ramamurthy, R. Jallepally, B. Ramachandran, C. Lai, A. Tjandra, N. Tam","doi":"10.1109/RTP.2004.1441962","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441962","url":null,"abstract":"Some RTP chamber non-uniformity is due to the lamp arrangement geometry. An internally written simulation program was written to reproduce this non-uniformity. The results of the simulation were successfully tested against experimental results. The simulation then lead to finding lamp types and lamp combination recipes which decrease overall non-uniformity in the RTP chamber by 40%","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128177296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integration of a long pulse laser thermal process for ultra shallow junction formation of CMOS devices","authors":"J. Venturini, M. Hernandez, K. Huet, C. Laviron, H. Akhouayri, T. Sarnet, J. Boulmer","doi":"10.1109/RTP.2004.1441939","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441939","url":null,"abstract":"We present results on ultra-shallow junction formation for the sub 65 nm CMOS node by means of a long pulse laser thermal process (LP-LTP). This method achieve to form abrupt and ultra-shallow junctions with low resistivities, but the different irradiated structures like transistor gates need to be preserved. To assess the integration of the laser process in the fabrication of a CMOS device, we studied the influence of optical coatings deposited before the laser irradiation in order to protect the structures. Different materials and coating thicknesses have been evaluated on blanket implanted wafers under a long pulse excimer laser (200 ns - 15 J) irradiation. The junctions have been characterized by 4-point probe, in-situ reflectivity, UV photometry and transmission electronic microscopy (TEM) pictures. Irradiations have also been performed on coated CMOS structures with 35 nm junctions to assess the integration of the process on a real structure. A selective etching scanning electronic microscope (SEM) view shows that a proper optical coating optimizes the coupling of the deposited laser energy and is promising for improving the integration of the laser activation process of future CMOS junctions","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"9 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113942399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Emissivity compensated pyrometry for specular silicon surfaces on the NIST RTP test bed","authors":"Benjamin K. Tsai, J. Bodycomb, D. DeWitt, K. Kreider, W. Kimes","doi":"10.1109/RTP.2004.1441958","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441958","url":null,"abstract":"Since pyrometric thermometry is a noncontact method, it has great promise as a technique for monitoring silicon wafers during rapid thermal processing (RTP). Absolute values of surface emissivity are required when making pyrometric temperature measurements. One approach to obtaining these values is the use of emissivity compensated pyrometry, where a reflectometer is integrated into the pyrometer to allow real-time emissivity measurement. While this technique has been successfully applied to metal organic chemical vapor deposition (MOCVD) of compound semiconductors, it has not been applied to RTP. Although such measurements require that the surface be a specular reflector, they promise real-time traceable temperature measurements that are independent of the nature of the wafer. Here we discuss measurement of wafer temperature for polished wafers and an initial attempt to measure a patterned wafer during heating inside the RTP test bed at the National Institute of Standards and Technology","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125625854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"In situ calibration of lightpipe radiometers for rapid thermal processing between 300/spl deg/C to 700/spl deg/C","authors":"W. Kimes, K. Kreider, D. Ripple, B. Tsai","doi":"10.1109/RTP.2004.1441956","DOIUrl":"https://doi.org/10.1109/RTP.2004.1441956","url":null,"abstract":"Many rapid thermal processing (RTP) tools are currently monitored and controlled with lightpipe radiometers (LPRTs), which have been limited to measuring temperatures above 500degC because of the low signal level below 500degC. New commercial LPRTs couple the optical detector directly to the lightpipe, eliminating the signal loss from optical cables. These cable-less light pipe radiometers (CLRTs) are capable of measuring temperature below 300degC. We present the results of calibrating a CLRT against our NIST thin-film thermocouple (TFTC) calibration wafer from 315degC to 700degC in our NIST RTP test bed. Below 550degC, light leakage from the heating lamps of the RTP tool introduced a significant error in the LPRT readings. By measuring the transient response of the CLRTs following rapid energizing of the heating lamps, we were able to differentiate between the radiance of the wafer and ambient chamber light. This allowed us to subtract the ambient chamber light from total measured radiation","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115602235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}