W. Yoo, T. Fukada, T. Murakami, K. Kang, J. Foggiato
{"title":"基于热壁的低温退火系统设计及其工艺应用","authors":"W. Yoo, T. Fukada, T. Murakami, K. Kang, J. Foggiato","doi":"10.1109/RTP.2004.1441941","DOIUrl":null,"url":null,"abstract":"A hot wall-based low temperature annealing system using resistively heated, stacked hot plates was designed and tested for low temperature (100~500degC) annealing applications for 200 mm and 300 mm wafers. The system is designed to process five wafers simultaneously for productivity enhancement purposes. Thermal properties of the system and wafer temperature profiles during low temperature annealing in stacked hot plates were characterized as a function of hot plate temperature. The stacked hot plate configuration with proper gap between wafer and surrounding hot plates makes convection heat transfer predominant and provides uniform and repeatable process results in the low temperature region. Process uniformity and repeatability of NiSi formation, Cu annealing, Al sintering, spin-on-dielectrics (SOD) anneal were confirmed in the temperature range of 100~500degC","PeriodicalId":261126,"journal":{"name":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of a hot wall-based low temperature annealing system and its process applications\",\"authors\":\"W. Yoo, T. Fukada, T. Murakami, K. Kang, J. Foggiato\",\"doi\":\"10.1109/RTP.2004.1441941\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A hot wall-based low temperature annealing system using resistively heated, stacked hot plates was designed and tested for low temperature (100~500degC) annealing applications for 200 mm and 300 mm wafers. The system is designed to process five wafers simultaneously for productivity enhancement purposes. Thermal properties of the system and wafer temperature profiles during low temperature annealing in stacked hot plates were characterized as a function of hot plate temperature. The stacked hot plate configuration with proper gap between wafer and surrounding hot plates makes convection heat transfer predominant and provides uniform and repeatable process results in the low temperature region. Process uniformity and repeatability of NiSi formation, Cu annealing, Al sintering, spin-on-dielectrics (SOD) anneal were confirmed in the temperature range of 100~500degC\",\"PeriodicalId\":261126,\"journal\":{\"name\":\"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RTP.2004.1441941\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTP.2004.1441941","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a hot wall-based low temperature annealing system and its process applications
A hot wall-based low temperature annealing system using resistively heated, stacked hot plates was designed and tested for low temperature (100~500degC) annealing applications for 200 mm and 300 mm wafers. The system is designed to process five wafers simultaneously for productivity enhancement purposes. Thermal properties of the system and wafer temperature profiles during low temperature annealing in stacked hot plates were characterized as a function of hot plate temperature. The stacked hot plate configuration with proper gap between wafer and surrounding hot plates makes convection heat transfer predominant and provides uniform and repeatable process results in the low temperature region. Process uniformity and repeatability of NiSi formation, Cu annealing, Al sintering, spin-on-dielectrics (SOD) anneal were confirmed in the temperature range of 100~500degC