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2010 53rd IEEE International Midwest Symposium on Circuits and Systems最新文献

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Process variation effects on ΔIDDQ testing of CMOS data converters 工艺变化对CMOS数据转换器ΔIDDQ测试的影响
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548793
R. Soundararajan, A. Srivastava, S. Yellampalli
{"title":"Process variation effects on ΔIDDQ testing of CMOS data converters","authors":"R. Soundararajan, A. Srivastava, S. Yellampalli","doi":"10.1109/MWSCAS.2010.5548793","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548793","url":null,"abstract":"We present, implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ?IDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if it causes the output frequency to deviate more than ±10% from the reference frequency. The output frequencies of the BICS for various (MOSIS) model parameters are simulated to check for the effect of process variation on the frequency deviation. A set of eight faults simulating manufacturing defects in CMOS data converters are injected using fault-injection transistors and tested successfully.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125836053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Systematic mixed even- and odd-mode modeling of parallel tightly coupled transmission lines 并联紧耦合输电线路的系统混合奇偶模建模
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548585
K. Murakami
{"title":"Systematic mixed even- and odd-mode modeling of parallel tightly coupled transmission lines","authors":"K. Murakami","doi":"10.1109/MWSCAS.2010.5548585","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548585","url":null,"abstract":"Systematic mixed even- and odd-mode modeling for analyzing parallel tightly coupled transmission lines is presented. This coupled line model is composed of even- and odd-mode equivalent lines. And, the numerical approach is based on the modified central difference (MCD) method. The voltage and current waves propagating along the parallel tightly coupled transmission lines are monitored by the time domain analysis method. For verification of the proposed modeling, a five-section 3-dB parallel coupled line is demonstrated dynamically. In addition, the S-parameters obtained from the pulse responses are compared with those of the commercial simulator.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126428707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Double diode modeling of time/temperature induced degradation of solar cells 时间/温度诱导太阳能电池退化的双二极管建模
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548809
P. Junsangsri, F. Lombardi
{"title":"Double diode modeling of time/temperature induced degradation of solar cells","authors":"P. Junsangsri, F. Lombardi","doi":"10.1109/MWSCAS.2010.5548809","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548809","url":null,"abstract":"This paper presents a simulation-based analysis of degradation of a solar cell as induced by temperature and/or time. Based on the double diode model (DDM) and using HSPICE, relationships are found between the parameters of the equivalent electrical circuit and efficiency, process variations and optimization in its operation. The results of this paper show that time, temperature and irradiance are of significance in DDM, because they affect the efficiency of a solar cell when degradation occurs.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127240926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A low power linearity-ratio-independent DAC with application in multi-bit ΔΣ ADCs 一种低功率线性比无关的DAC，应用于多位ΔΣ adc
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548734
Yu Song, Zhe Gao, Z. Ignjatovic
{"title":"A low power linearity-ratio-independent DAC with application in multi-bit ΔΣ ADCs","authors":"Yu Song, Zhe Gao, Z. Ignjatovic","doi":"10.1109/MWSCAS.2010.5548734","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548734","url":null,"abstract":"A low power linearity-ratio-independent DAC for ΔΣ data converters is proposed in this paper. By using a gainboosted sub-threshold inverter as an amplifier, circuit power consumption is decreased significantly. The sensitivity of the differential DAC output linearity on circuit mismatches is reduced by using mutually-referred inputs. In a 0.13um CMOS technology, Monte-Carlo analysis and transistor-level simulations show that with 660µW power consumption, the DAC demonstrates 16 bit linearity at an 8MHz output rate. Its differential output swing is about 1.2V with a 1.2V power supply. A multi-bit ΔΣ modulator is designed using the proposed DAC.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127690075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A composite CMOS pair and an adjoint 复合CMOS对及其伴随
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548760
Haoyu Wang, R. Newcomb
{"title":"A composite CMOS pair and an adjoint","authors":"Haoyu Wang, R. Newcomb","doi":"10.1109/MWSCAS.2010.5548760","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548760","url":null,"abstract":"The CMOS transistor pair of Seevinck and Wassenaar is reviewed. Beside the properties previously reported it is shown by calculating the effective SPICE parameter LAMBDA that the channel length modulation is improved. The analytic derivation is verified by simulations of both P and N type pairs. It is also shown that for small effective gate voltages a negative incremental resistance is obtained for which the adjoint is found following the theory of Professor Swamy.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114190928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scalable interconnect networks for Discrete Cosine Transforms (DCT) for mobile and multimedia application 用于移动和多媒体应用的离散余弦变换(DCT)的可扩展互连网络
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548713
A. Hussein, A. Suleiman, Nabil Kerkiz, D. Akopian
{"title":"Scalable interconnect networks for Discrete Cosine Transforms (DCT) for mobile and multimedia application","authors":"A. Hussein, A. Suleiman, Nabil Kerkiz, D. Akopian","doi":"10.1109/MWSCAS.2010.5548713","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548713","url":null,"abstract":"Scalable architectures were proposed for Discrete Cosine Transform (DCT). Number of processing elements (PE) can be reduced significantly using partial column structure for computing the DCT transform. This feature is very desirable for multimedia applications usage in handheld devices. As per transform computation, data reordering is required between stages (columns) where intermediate computed values are saved in memory-like temporary locations called FIFO's. A scalable interconnect network for both global and local data reordering and its implementation is presented in this paper. Scalability is based on transform size and desired number of processing elements (PE). The structure gives choice flexibility of throughput vs. complexity (cost and area.) of the overall system.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122300014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design technique for two-directional recursive filters 双向递归滤波器的设计技术
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548862
R. Matei
{"title":"Design technique for two-directional recursive filters","authors":"R. Matei","doi":"10.1109/MWSCAS.2010.5548862","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548862","url":null,"abstract":"This work approaches the design of a class of 2D recursive filters, with a two-directional orientation-selective frequency response. We propose two design methods based on a given 1D digital prototype filter and frequency transformations, one completely analytical, including the bilinear transform, and another which uses a numerical approximation stage. These filters may find useful applications in image processing, like detecting lines with a given orientation from an image, as we show through simulation results. The resulted filters are very efficient, being at the same time of low complexity and relatively high selectivity. Simulation results are provided which show their image filtering capabilities.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121983955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design techniques for remote frequency calibration of passive wireless microsystems 无源无线微系统的远程频率校准设计技术
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548665
F. Yuan
{"title":"Design techniques for remote frequency calibration of passive wireless microsystems","authors":"F. Yuan","doi":"10.1109/MWSCAS.2010.5548665","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548665","url":null,"abstract":"This paper provides an overview and in-depth examination of the state-of-the-art of remote frequency calibration of the system clock of passive wireless microsystems. Frequency calibration using the carrier and the envelope of received RF signals, frequency calibration using injection-locked division, carrier injection-locking, digital trimming, envelope injection-locking with integrating feedback are investigated. The advantages and design constraints of each frequency calibration method are examined in detail. The performance of these frequency calibration methods are compared.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131258629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simple low voltage, low power implementations of circuits for VT extraction 简单的低电压、低功耗实现VT提取电路
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548857
J. Ramírez-Angulo, Venkata Sailaja Kasaraneni, R. Carvajal, A. López-Martín
{"title":"Simple low voltage, low power implementations of circuits for VT extraction","authors":"J. Ramírez-Angulo, Venkata Sailaja Kasaraneni, R. Carvajal, A. López-Martín","doi":"10.1109/MWSCAS.2010.5548857","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548857","url":null,"abstract":"Two simple implementations of circuits to extract V<inf>T</inf> are introduced. They are independent of body effect and operate on a single supply voltage V<inf>DD</inf> of less than two gate-source drops. Experimental and simulation results verify the circuit operation with a power dissipation P=60µA and with single supply V<inf>DD</inf>=1.4V in 0.5µm CMOS technology and with variations of the extracted threshold voltage of less than 0.2mV for V<inf>DD</inf> changing from 1.4V to 2.5V.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122689182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low phase noise, wide range QVCO for MICS, and ISM applications 低相位噪声，适用于MICS和ISM应用的宽范围QVCO
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548885
N. Haghighi, K. Raahemifar
{"title":"A low phase noise, wide range QVCO for MICS, and ISM applications","authors":"N. Haghighi, K. Raahemifar","doi":"10.1109/MWSCAS.2010.5548885","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548885","url":null,"abstract":"A Quadrature Voltage Controlled Oscillator (QVCO) has been designed and simulated at 0.18µm technology, 1.8 V supply voltage. The design is aimed for MICS/ ISM devices. The design offers a small size, low power consumption, low phase noise, and wide frequency range (200-827 MHz) of operation. The obtained phase noise (at 37° C) @ 160 KHz offset for 404.7 MHz oscillation is −100dBc/Hz and for 433 MHz oscillation at 160KHZ offset is at −99.5 dBc/Hz with 0.9mW power consumption.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123862536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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