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2010 53rd IEEE International Midwest Symposium on Circuits and Systems最新文献

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High resolution low power 0.6µm CMOS 40MHz dynamic latch comparator 高分辨率低功耗0.6µm CMOS 40MHz动态锁存比较器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548824
Carlos J. Solis, G. Ducoudray
{"title":"High resolution low power 0.6µm CMOS 40MHz dynamic latch comparator","authors":"Carlos J. Solis, G. Ducoudray","doi":"10.1109/MWSCAS.2010.5548824","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548824","url":null,"abstract":"In order to diminish circuit complexity and power dissipation, the simple configuration of the dynamic latch comparator is revisited. This paper proposes and analyzes a comparator that consists of a preamplifier using negative resistance as a load and a double regenerative dynamic latch. A discussion of the dynamic latch is presented and the effect of transistor sizes in the time constant and the offset voltage is explained briefly. The comparator is designed in a 0.6µm CMOS technology. Monte Carlo simulation using Virtuoso® Spectre shows that the comparator has a resolution of 1.8mV and dissipates 750µW of power when working at 40MHz.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121701544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Power-performance versus algorithmic trade-offs in the implementation of wireless multimedia terminals 无线多媒体终端实现中的功率性能与算法权衡
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548723
S. Nooshabadi
{"title":"Power-performance versus algorithmic trade-offs in the implementation of wireless multimedia terminals","authors":"S. Nooshabadi","doi":"10.1109/MWSCAS.2010.5548723","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548723","url":null,"abstract":"Circuit design for wireless applications generally involves achieving a certain level of processing speed, dictated by the data transmission rate and algorithmic performance, while minimizing the energy dissipation. This paper discusses some of the circuit techniques that help to achieve this goal. We show that power reduction in a multimedia system involves trade-offs at the algorithmic, algebraic, architectural, and circuit levels of abstraction.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"616 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123949729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An efficient and reliable clustering algorithm for wireless sensor actor networks (WSANs) 一种高效可靠的无线传感器行为网络聚类算法
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548829
M. Khan, G. Shah, M. Ahsan, M. Sher
{"title":"An efficient and reliable clustering algorithm for wireless sensor actor networks (WSANs)","authors":"M. Khan, G. Shah, M. Ahsan, M. Sher","doi":"10.1109/MWSCAS.2010.5548829","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548829","url":null,"abstract":"Wireless sensor and actor network (WSAN) is formed by the collaboration of micro-sensor and actor node. Whenever there is any special event i.e., fire, earth quake, flood or enemy attack in the network, sensor nodes have responsibility to sense it and send information towards an actor. The actor node is responsible to take prompt decision and react accordingly. Sensor nodes have limited resources which causes the deduction in network life time. Therefore it is important to efficiently utilize these resources so that the network life may extend up to its maximum level. Clustering is a new approach to efficiently utilize the energy of sensor nodes. Where the whole network is divided into group. There is a head election in each group of sensors. The CH is responsible to gather sensed data from its underlying sensors and forward it towards actor node for necessary action instead every sensor send data to actor. This approach helps to reduce the network traffic as well as resources utilization. In this paper we propose a new energy efficient and reliable clustering algorithm called Actor directed clustering Protocol (ADCP) that increases the life time of network. Our simulation results show that using ADCP the cluster head efficiently deliver data to an actor node with minimum delay that helps for taking a quick action and control the attack in its initial stage.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122364936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
LNA automatic synthesis and characterization for accurate RF system-level simulation 用于精确射频系统级仿真的LNA自动合成和表征
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548785
D. Haghighitalab, M. Vasilevski, H. Aboushady
{"title":"LNA automatic synthesis and characterization for accurate RF system-level simulation","authors":"D. Haghighitalab, M. Vasilevski, H. Aboushady","doi":"10.1109/MWSCAS.2010.5548785","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548785","url":null,"abstract":"In this paper, we propose an automatic design procedure for the synthesis of a cascode LNA with inductive source degeneration. The proposed method is based on the precise characterization of noise figure, input impedance and gain. The design procedure is implemented in a C++ environment using a BSIM3v3-based tool for transistor sizing and a symbolic computation tool for circuit characterization. SystemC AMS can then be used to perform a system level simulation of a complete RF receiver using precise model of the LNA. Considering the complete equivalent model for the transistors and the inductors, two LNAs operating at 2.4 GHz and 935 MHz are synthesized and characterized for a 130 nm CMOS process. The generated accurate model is then used in a high-level simulation of a complete QPSK-based RF receiver to study the effect of the LNA noise figure on the Bit Error Rate of the receiver.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129736405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Model study of 1T-1STT MTJ memory arrays for embedded applications 嵌入式应用1T-1STT MTJ存储阵列模型研究
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548591
A. Raychowdhury
{"title":"Model study of 1T-1STT MTJ memory arrays for embedded applications","authors":"A. Raychowdhury","doi":"10.1109/MWSCAS.2010.5548591","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548591","url":null,"abstract":"The use of current to switch nanomagnets has opened up opportunities for using spin-torque-transfer (STT) based magnetic memories in embedded applications. This paper presents a design space exploration of 1T-1STT MTJ arrays for embedded applications, under variations and disturbs conditions.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130557770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Area optimized multiplier using flow retiming and input data folding 面积优化乘数使用流量重定时和输入数据折叠
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548769
Khaldoun Bataineh, Amjad D. Odetallah, A. Suleiman, A. Hussein
{"title":"Area optimized multiplier using flow retiming and input data folding","authors":"Khaldoun Bataineh, Amjad D. Odetallah, A. Suleiman, A. Hussein","doi":"10.1109/MWSCAS.2010.5548769","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548769","url":null,"abstract":"This paper presents a 16-bit area enhanced modular multiplier. The proposed multiplier uses 4-bit multipliers as building blocks. Significant area reduction is realized via hardware reuse. Reduction of 4-bit multiplier instances was achieved using multiplication flow retiming (iteration) and input operands reordering (folding) techniques. Implementation results show that the proposed architecture has area advantage over existing ones such as Wallace and 4-bit Modular multipliers.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"20 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130959801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-band quadrature generator based on the virtual LO phase shifting technique 基于虚拟本相移技术的多波段正交发生器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548791
F. Cannone, G. Avitabile, G. Coviello, D. Cascella
{"title":"Multi-band quadrature generator based on the virtual LO phase shifting technique","authors":"F. Cannone, G. Avitabile, G. Coviello, D. Cascella","doi":"10.1109/MWSCAS.2010.5548791","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548791","url":null,"abstract":"The paper describes a new digitally programmable multi-band precise quadrature generator. The proposed approach leads to high-phase resolution joint to uniform performances in all the sub-bands of synthesis. It is easily scalable in frequency and suitable to implement any calibration technique to compensate the typical phase imbalance generated in the front end. The theory governing the quadrature generation and the operation of the used multi-band VCO are described. A prototype reporting a phase error less than 0.5° over the two sub-bands confirming the architecture capabilities is finally reported.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130230189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS voltage-to-frequency converter with output frequency range programmability 一种输出频率范围可编程的CMOS电压-频率转换器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548805
C. Azcona, B. Calvo, N. Medrano, S. Celma, F. Aznar
{"title":"A CMOS voltage-to-frequency converter with output frequency range programmability","authors":"C. Azcona, B. Calvo, N. Medrano, S. Celma, F. Aznar","doi":"10.1109/MWSCAS.2010.5548805","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548805","url":null,"abstract":"This paper represents the design of a low-cost programmable CMOS voltage-to-frequency converter suitable for wireless sensor nodes signal conditioning. Designed in a 0.18µm CMOS technology supplied at 1.8V, it operates for a 0.0-1.6V input voltage with power consumption below 0.41mW. Three different output frequency ranges can be digitally selected: 0.0 to 0.5MHz, 0.0 to 1MHz or 0.0 to 1.5MHz. The accuracy achieved is better than 3 %, with linearity errors below 0.04 %.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130234676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SIDO buck converter with independent outputs 具有独立输出的SIDO降压转换器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548555
H. Eachempatti, S. Ganta, J. Silva-Martínez, H. Martínez-García
{"title":"SIDO buck converter with independent outputs","authors":"H. Eachempatti, S. Ganta, J. Silva-Martínez, H. Martínez-García","doi":"10.1109/MWSCAS.2010.5548555","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548555","url":null,"abstract":"The portable electronics market is rapidly migrating towards more compact devices requiring multiple high-integrity high-efficiency voltage supplies for empowering the systems. This paper demonstrates a single inductor used in a buck converter with two output voltages from an input battery with voltage of value 3V. The main target is low cross regulation between the two outputs to supply independent load current levels while maintaining desired output voltage values well within a ripple that is set by adaptive hysteresis levels. A reverse current detector to avoid negative current flowing through the inductor prevents efficiency degradation at light load.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125517218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Intel LVS logic in CNT technology 碳纳米管技术中的英特尔LVS逻辑
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548549
Xuan Zeng, Bao Liu, Zhen Cao, Jun Tao, Philip Wong, Pushan Tang
{"title":"Intel LVS logic in CNT technology","authors":"Xuan Zeng, Bao Liu, Zhen Cao, Jun Tao, Philip Wong, Pushan Tang","doi":"10.1109/MWSCAS.2010.5548549","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548549","url":null,"abstract":"In this paper, we systematically evaluate combinational logic families for CNT technology implementation for a variety of logic families, signal transition times, and transistor parameters. We compare CMOS static logic, and Intel LVS logic in CNT and silicon technologies by SPICE simulation based on Predictive Technology Model and Stanford compact CNFET models. We observe that CMOS static logic in CNT technology achieves limited (e.g., 3.44×) performance improvement and (e.g., 3.83×) power consumption reduction, while Intel LVS logic achieves more significant performance improvement and orders-of-magnitude of power consumption reduction. Intel LVS logic achieves an average of 4.02× performance improvement and 1137.64× power consumption reduction compared with CMOS static logic in silicon for the same combinational logic functions and input signals, and enhanced reliability, making it an ideal combinational logic circuit paradigm in CNT technology.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126376032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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