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2010 53rd IEEE International Midwest Symposium on Circuits and Systems最新文献

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Image sensor readout circuitry supporting the analog computation of large vertical surrounds 支持大型垂直环绕的模拟计算的图像传感器读出电路
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548747
Madhu Latha Reddy Vatte, F. Hassan, J. Carletta, R. Veillette
{"title":"Image sensor readout circuitry supporting the analog computation of large vertical surrounds","authors":"Madhu Latha Reddy Vatte, F. Hassan, J. Carletta, R. Veillette","doi":"10.1109/MWSCAS.2010.5548747","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548747","url":null,"abstract":"A logarithmic CMOS image sensor is proposed with a readout circuit that allows the direct calculation of a weighted average of pixels in a column. The kernel weights are controlled through bias voltages in a set of variable-gain current mirrors. A detailed description of the circuit topology and design is given. The circuitry was simulated using 1.2°m CMOS technology. The simulation shows that inaccuracies in the effective kernel weights due to changes in loading as the photodiode currents for individual pixels vary result in errors of no more than 0.88% in the computed vertical averages for an example 33-pixel Gaussian kernel. The analog computation of the vertical averages eliminates the need for the buffer memory that is ordinarily required when implementing two-dimensional image filters entirely in digital hardware.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116151949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A differential design for C-elements and NCL gates c -元件和NCL栅极的差分设计
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548905
Steve Y. Yancey, S. Smith
{"title":"A differential design for C-elements and NCL gates","authors":"Steve Y. Yancey, S. Smith","doi":"10.1109/MWSCAS.2010.5548905","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548905","url":null,"abstract":"This paper demonstrates the performance, area and supply voltage scaling advantages of a Differential Cascode Voltage-Switch Logic (DCVSL)-like design over previous methods for designing C-elements. The DCVSL-like method is then applied to the design of arbitrary NULL Convention Logic (NCL) gates, which have hysteresis state-holding capability.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123316041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
MAC hardware platform for RF-MIMO WLAN 用于RF-MIMO WLAN的MAC硬件平台
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548838
K. Tittelbach-Helmrich, E. Miletic, P. Wcislek, Z. Stamenkovic
{"title":"MAC hardware platform for RF-MIMO WLAN","authors":"K. Tittelbach-Helmrich, E. Miletic, P. Wcislek, Z. Stamenkovic","doi":"10.1109/MWSCAS.2010.5548838","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548838","url":null,"abstract":"The paper describes a hardware solution for the IEEE 802.11 MAC (Medium Access Control) layer in an RF-MIMO WLAN. Architecture and implementation details of the MAC processor including a hardware accelerator and a 16-bit MAC-PHY interface are presented. The proposed hardware solution is tested and verified using a PHY link emulator.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123576203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High resolution low power 0.6µm CMOS 40MHz dynamic latch comparator 高分辨率低功耗0.6µm CMOS 40MHz动态锁存比较器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548824
Carlos J. Solis, G. Ducoudray
{"title":"High resolution low power 0.6µm CMOS 40MHz dynamic latch comparator","authors":"Carlos J. Solis, G. Ducoudray","doi":"10.1109/MWSCAS.2010.5548824","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548824","url":null,"abstract":"In order to diminish circuit complexity and power dissipation, the simple configuration of the dynamic latch comparator is revisited. This paper proposes and analyzes a comparator that consists of a preamplifier using negative resistance as a load and a double regenerative dynamic latch. A discussion of the dynamic latch is presented and the effect of transistor sizes in the time constant and the offset voltage is explained briefly. The comparator is designed in a 0.6µm CMOS technology. Monte Carlo simulation using Virtuoso® Spectre shows that the comparator has a resolution of 1.8mV and dissipates 750µW of power when working at 40MHz.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121701544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Design technique for two-directional recursive filters 双向递归滤波器的设计技术
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548862
R. Matei
{"title":"Design technique for two-directional recursive filters","authors":"R. Matei","doi":"10.1109/MWSCAS.2010.5548862","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548862","url":null,"abstract":"This work approaches the design of a class of 2D recursive filters, with a two-directional orientation-selective frequency response. We propose two design methods based on a given 1D digital prototype filter and frequency transformations, one completely analytical, including the bilinear transform, and another which uses a numerical approximation stage. These filters may find useful applications in image processing, like detecting lines with a given orientation from an image, as we show through simulation results. The resulted filters are very efficient, being at the same time of low complexity and relatively high selectivity. Simulation results are provided which show their image filtering capabilities.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121983955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
All-pass RF phase shifter for bio-antennas 生物天线全通射频移相器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548648
Mohammad Safar, R. Newcomb
{"title":"All-pass RF phase shifter for bio-antennas","authors":"Mohammad Safar, R. Newcomb","doi":"10.1109/MWSCAS.2010.5548648","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548648","url":null,"abstract":"An RF phase shifter is designed using the all-pass filter topology. The shifter will be used in bio-antenna array circuits for an operating frequency of 1GHz. The phase shifter was simulated using the AMI 0.5µm CMOS technology. Using a 3V voltage supply, two phase shift ranges were achieved with a voltage gain of approximately 5dB. The phase shifting was achieved using an analog bias voltage with voltage range from 0.4V to 0.8V. The maximum power consumption of the phase shifter was 339µW.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121052187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power-performance versus algorithmic trade-offs in the implementation of wireless multimedia terminals 无线多媒体终端实现中的功率性能与算法权衡
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548723
S. Nooshabadi
{"title":"Power-performance versus algorithmic trade-offs in the implementation of wireless multimedia terminals","authors":"S. Nooshabadi","doi":"10.1109/MWSCAS.2010.5548723","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548723","url":null,"abstract":"Circuit design for wireless applications generally involves achieving a certain level of processing speed, dictated by the data transmission rate and algorithmic performance, while minimizing the energy dissipation. This paper discusses some of the circuit techniques that help to achieve this goal. We show that power reduction in a multimedia system involves trade-offs at the algorithmic, algebraic, architectural, and circuit levels of abstraction.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"616 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123949729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 36-mW 320-MHz CMOS continuous-time sigma-delta modulator with 10-MHz bandwidth and 12-bit resolution 一个36-mW 320-MHz CMOS连续时间sigma-delta调制器，带宽10-MHz，分辨率12位
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548717
Kuo-Che Hong, H. Chiueh
{"title":"A 36-mW 320-MHz CMOS continuous-time sigma-delta modulator with 10-MHz bandwidth and 12-bit resolution","authors":"Kuo-Che Hong, H. Chiueh","doi":"10.1109/MWSCAS.2010.5548717","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548717","url":null,"abstract":"A wide-bandwidth low-power CT ΔΣ modulator with 10MHz signal bandwidth is implemented in TSMC 0.18 µm CMOS process in this paper. To realize such application scenario, the proposed modulator comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time derivator structure. The simulation result achieves above 74-dB SNDR (12 ENOB) over a 10-MHz signal band. The power dissipation is 36mW from a 1.8-V supply and the energy per conversion is 235fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125336128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Intel LVS logic in CNT technology 碳纳米管技术中的英特尔LVS逻辑
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548549
Xuan Zeng, Bao Liu, Zhen Cao, Jun Tao, Philip Wong, Pushan Tang
{"title":"Intel LVS logic in CNT technology","authors":"Xuan Zeng, Bao Liu, Zhen Cao, Jun Tao, Philip Wong, Pushan Tang","doi":"10.1109/MWSCAS.2010.5548549","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548549","url":null,"abstract":"In this paper, we systematically evaluate combinational logic families for CNT technology implementation for a variety of logic families, signal transition times, and transistor parameters. We compare CMOS static logic, and Intel LVS logic in CNT and silicon technologies by SPICE simulation based on Predictive Technology Model and Stanford compact CNFET models. We observe that CMOS static logic in CNT technology achieves limited (e.g., 3.44×) performance improvement and (e.g., 3.83×) power consumption reduction, while Intel LVS logic achieves more significant performance improvement and orders-of-magnitude of power consumption reduction. Intel LVS logic achieves an average of 4.02× performance improvement and 1137.64× power consumption reduction compared with CMOS static logic in silicon for the same combinational logic functions and input signals, and enhanced reliability, making it an ideal combinational logic circuit paradigm in CNT technology.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126376032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Process variation effects on ΔIDDQ testing of CMOS data converters 工艺变化对CMOS数据转换器ΔIDDQ测试的影响
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548793
R. Soundararajan, A. Srivastava, S. Yellampalli
{"title":"Process variation effects on ΔIDDQ testing of CMOS data converters","authors":"R. Soundararajan, A. Srivastava, S. Yellampalli","doi":"10.1109/MWSCAS.2010.5548793","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548793","url":null,"abstract":"We present, implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ?IDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if it causes the output frequency to deviate more than ±10% from the reference frequency. The output frequencies of the BICS for various (MOSIS) model parameters are simulated to check for the effect of process variation on the frequency deviation. A set of eight faults simulating manufacturing defects in CMOS data converters are injected using fault-injection transistors and tested successfully.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125836053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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