{"title":"Integrate and dump based VGA with an embedded programmable complex analog FIR filter","authors":"M. Omar, A. Emira, M. Dessouky","doi":"10.1109/MWSCAS.2010.5548719","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548719","url":null,"abstract":"This paper presents a novel VGA (Variable Gain Amplifier) with an embedded complex (polyphase) analog FIR (Finite Impulse Response) filter architecture. The idea is based on a modified version of the integrate and dump circuit. The proposed modifications allow altering the frequency response of the circuit without significantly increasing the circuit complexity along with maintaining acceptable gain control range, noise and linearity. The proposed circuit was designed using 0.13 µm CMOS technology. It consumes 365 µA from 1.2 V supply with an input referred noise of 50 nV over √Hz.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126315587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Bryant, Sourabh Ravindran, N. Magotra, S. Northrup
{"title":"Real-time implementation of a chest-worn accelerometer based heart monitoring system","authors":"D. Bryant, Sourabh Ravindran, N. Magotra, S. Northrup","doi":"10.1109/MWSCAS.2010.5548828","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548828","url":null,"abstract":"This paper presents the real-time implementation of an approach for monitoring the heart using a single accelerometer. The implementation described is based on an algorithmic approach that has been shown to successfully remove motion artifacts from accelerometer based heart signal measurements. A driving factor in this project is the need for low-cost heart rate monitoring as part of a personal monitoring system for use world-wide. The digital signal processor (DSP) chosen for the implementation was Texas Instruments (TI) TMS320C5505 DSP in order to reduce the power requirement of the specific implementation thereby conserving battery life. The TMS320C5505 CPU can operate on 1.05V and the chip architecture has been highly optimized for energy efficiency.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116063672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modified Elmore delay model for VLSI interconnect","authors":"A. K. Mal, A. Dhar","doi":"10.1109/MWSCAS.2010.5548693","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548693","url":null,"abstract":"This paper describes a simple method of calculating delay of an RC ladder which is often encountered in VLSI interconnect analysis. The method first deals with a specific case where R and C are identical and the transfer function in closed form, is derived for arbitrary number of stages. The roots of the transfer function is then found in closed form and from there exact delay calculation is made. For arbitrary RC values, the derived method is combined with Elmore delay and a modified simple delay metric is proposed. For a first order approximation, the proposed method is matched with Elmore model and results are found more accurate at same computational requirement.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115972034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of universal logic gate targeting minimum wire-crossings in QCA logic circuit","authors":"B. Sen, Anik Sengupta, M. Dalui, B. Sikdar","doi":"10.1109/MWSCAS.2010.5548873","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548873","url":null,"abstract":"Wire crossings limit the performance of a logic circuit in Quantum-Dot Cellular Automata (QCA) based design. Minimization of wire-crossings is, therefore, of prime importance in the current nanotechnology, susceptible to high error rates. This work proposes a QCA (Quantum-Dot Cellular Automata) logic gate (UQCALG) realizing the universal functions. The design of UQCALG is based on the coupled Majority Minority (CMVMIN) QCA structure with the target to reduce wire crossings as well as the number of clock cycles required to operate a QCA circuit. The experimental designs establish that the UQCALG can lead to the cost effective design of QCA logic circuits that may not be possible with conventional ULG (Universal Logic Gate).","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125107746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Advancements on crossbar-based nanoscale reconfigurable computing Platforms","authors":"Bao Liu","doi":"10.1109/MWSCAS.2010.5548550","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548550","url":null,"abstract":"A recently proposed carbon nanotube (CNT) crossbar nano-architecture provides the first purely CNT-based platform for nanoscale computing systems. In this paper, I present a number of degrees of freedom in optimizing this nano-architecture, and evaluate several variant nanoscale computing platforms based on a combination of floating-gate transistor arrays and programmable vias. Experimental results based on Stanford compact CNFET model show that proper device integration, cell granularity, and logic family (e.g., reconfigurable CMOS static logic in floating-gate transistor arrays) lead to an optimized nanoscale computing platform, with reduced manufacture complexity, improved logic density, improved performance, and reduced power consumption.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122489402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Subthreshold CMOS active inductors with applications to low-power injection-locked oscillators for passive wireless microsystems","authors":"Yushi Zhou, F. Yuan","doi":"10.1109/MWSCAS.2010.5548661","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548661","url":null,"abstract":"This paper investigates gyrator-C active inductors in weak inversion. An injection-locked active inductor oscillator in weak inversion designed in IBM-0.13µm 1.2V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM4 device models. The injection-locking signal is generated using a generic ring oscillator. Simulation results show that the phase noise of the injection-locked active inductor VCO is much smaller as compared with that of the same active inductor VCO but without injection-locking. Also observed is that the phase noise of the injection-locked active inductor VCO is approximately the same as that of injection ring VCO when frequency offset is less than 200 kHz and increases when frequency offset is beyond 200 kHz. The power consumption of the oscillator is 776 nW at 13 MHz. With the proper biasing voltage, the tuning range of active inductor VCO is from 6.5 MHz to 34.6 MHz. The layout area of the injection-locked oscillator including bond pads and an output buffer is 0.67 mm2. The silicon consumption of the core of the oscillator is only 13 µm2.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133449398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A high-speed frequency acquisition PLL using phase frequency detector with variable gain","authors":"J. Yau, S. Tu","doi":"10.1109/MWSCAS.2010.5548571","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548571","url":null,"abstract":"Conventional phase-locked loops (PLL) with a tri-state phase frequency detector (PFD) and a charge pump (CP) typically suffer long locking time in video applications due to low reference frequency (30K Hz∼150kHz). In this paper, we propose a novel multi-state phase frequency detector with variable gain which can efficiently reduce the locking time. The post-layout simulation results indicate that the locking time of the PLL using the proposed novel multi-state PFD can be reduced about 49% compared with conventional PFDs.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134494786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Robust design of adaptive neural controllers for unknown nonlinear systems","authors":"Ziqian Liu, R. E. Torres, Miltiadis Kotinis","doi":"10.1109/MWSCAS.2010.5548804","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548804","url":null,"abstract":"In this paper, we extend our previous research results from the stabilization of dynamic neural networks to the stabilization of unknown nonlinear systems, and present an approach of H∞ control for nonlinear systems via dynamic neural networks. The proposed H∞ controller is intended to attenuate the adverse impact of modeling error, considered as a disturbance, to a prescribed level with stability margins. A numerical example demonstrates the performance of stabilizing control on an unstable unknown nonlinear system.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133075714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Abdelhak, C. S. Gurram, Soumik Ghosh, M. Bayoumi
{"title":"Energy-balancing task allocation on wireless sensor networks for extending the lifetime","authors":"S. Abdelhak, C. S. Gurram, Soumik Ghosh, M. Bayoumi","doi":"10.1109/MWSCAS.2010.5548700","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548700","url":null,"abstract":"Extending the wireless sensor network's lifetime has been the aim of several research efforts. Distributed in-network processing arises as a viable solution to extend the network's lifetime. It avoids assigning heavy computations to a single node which might otherwise lead to its significant energy depletion. Task scheduling and allocation play a major role in the efficiency of the distribution. This work proposes EBSEL, an e̲nergy-b̲alancing task s̲cheduling and allocation heuristic whose main purpose is to e̲xtend the network's l̲ifetime, through energy balancing. Balancing the energy consumption among the nodes can help avoid the disintegration of the network where some nodes die unnecessarily, while others still have high energy reserve. EBSEL was extensively simulated on random task graphs and on a task graph of a real-world application. Compared to related work, EBSEL achieved more than 50% increase in lifetime and up to 5% energy savings per iteration.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115677825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A composite CMOS pair and an adjoint","authors":"Haoyu Wang, R. Newcomb","doi":"10.1109/MWSCAS.2010.5548760","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548760","url":null,"abstract":"The CMOS transistor pair of Seevinck and Wassenaar is reviewed. Beside the properties previously reported it is shown by calculating the effective SPICE parameter LAMBDA that the channel length modulation is improved. The analytic derivation is verified by simulations of both P and N type pairs. It is also shown that for small effective gate voltages a negative incremental resistance is obtained for which the adjoint is found following the theory of Professor Swamy.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114190928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}