Advancements on crossbar-based nanoscale reconfigurable computing Platforms

Abstract

A recently proposed carbon nanotube (CNT) crossbar nano-architecture provides the first purely CNT-based platform for nanoscale computing systems. In this paper, I present a number of degrees of freedom in optimizing this nano-architecture, and evaluate several variant nanoscale computing platforms based on a combination of floating-gate transistor arrays and programmable vias. Experimental results based on Stanford compact CNFET model show that proper device integration, cell granularity, and logic family (e.g., reconfigurable CMOS static logic in floating-gate transistor arrays) lead to an optimized nanoscale computing platform, with reduced manufacture complexity, improved logic density, improved performance, and reduced power consumption.