{"title":"Low-power switched-capacitor integrator for delta-sigma ADCs","authors":"Tao Wang, G. Temes","doi":"10.1109/MWSCAS.2010.5548741","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548741","url":null,"abstract":"A new low-power switched-capacitor integrator is proposed for high-resolution ΔΣ ADCs. Compared to the conventional switched-capacitor integrator, it achieves much lower power dissipation for the same noise specifications. To verify the effectiveness of the new integrator, and to compare it with the conventional one, a third-order delta-sigma modulator was simulated. A detailed comparison between the conventional SC integrator and the proposed SC integrator is also presented.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116638612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Athavale, Jayanand Asok Kumar, Shobha Vasudevan
{"title":"A scalable approach for throughput estimation of timing speculation designs","authors":"V. Athavale, Jayanand Asok Kumar, Shobha Vasudevan","doi":"10.1109/MWSCAS.2010.5548771","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548771","url":null,"abstract":"Timing speculation is a ‘better-than-worst-case’ design methodology that tunes a digital circuit to its common-case delay. The average throughput of a speculation-based circuit can be estimated using the probability with which input patterns result in timing errors. In this paper, we present a scalable approach to compute the exact probabilities of the occurrence of timing errors at the gate level. We use Timed Characteristic Functions (TCFs) to compute the exact values of the probabilities. In order to improve the scalability, we decompose large circuits into smaller sub-circuits and restrict the TCF computation to these sub-circuits. Instead of substituting the expression for TCF of one sub-circuit into another, we propagate only the computed error probabilities. We demonstrate our technique on gate level combinational circuits from MCNC benchmarks.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116684432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel preamble for OFDM symbol synchronization that can outperform PN-based preambles in narrowband channels","authors":"Maher Umari, K. Razazian, O. Petrovska","doi":"10.1109/MWSCAS.2010.5548699","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548699","url":null,"abstract":"A new preamble for correlation-based symbol synchronization schemes in narrowband channels is presented. While autocorrelation properties of Pseudo-noise (PN) sequence preambles make them very well suited for symbol synchronization in wideband channels, the same is not necessarily true in narrowband channels. In fact, a narrowband preamble that has a cross-correlation - between the input and output of the channel - with smaller side lobes than a PN-based preamble can lead to better symbol synchronization in narrowband channels. Such a preamble is presented along with simulation results showing the performance of a typical symbol synchronization scheme when using the proposed narrowband preamble vs. a PN-based preamble.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116774001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low power software techniques for embedded systems running real time operating systems","authors":"Daniel E. Mera, N. Santiago","doi":"10.1109/MWSCAS.2010.5548830","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548830","url":null,"abstract":"Power consumption is an important constraint in embedded systems running real time operating systems (RTOS). This study proposes an evaluation of significance of the joint effect of possible factors in the power consumption of RTOS running on small and medium scale embedded systems. Design of experiments techniques (DOE) were used to identify the impact in the power consumption of the system. A case of study is presented with optimizations oriented to dynamic frequency scaling and memory management were applied to FreeRTOS. Experiments allowed us to find relationships between the type of architecture, the workload, and OS optimizations in power reduction.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121335358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Abouzied, Hattem Osman, A. Mohieldin, A. Emira, A. Soliman
{"title":"An integrated SAW-less narrowband RF front-end","authors":"M. Abouzied, Hattem Osman, A. Mohieldin, A. Emira, A. Soliman","doi":"10.1109/MWSCAS.2010.5548913","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548913","url":null,"abstract":"In this paper an integrated SAW-less narrowband RF front-end for direct conversion wireless receivers is presented. The analysis of the feedback system shows a shift of the center frequency fRX for the overall RF bandpass filter from its nominal value fLO. The proposed architecture incorporates a notch filter at 2fLO to insure that there is no shift in fRX. The design has been implemented in 65nm CMOS process. It consumes 44mA from a single 1.2V supply. Simulation results show a rejection of more than 15dB in a bandwidth of +/−500MHz around 2GHz due to the additional feedback loop. The theoretical and simulation results are in close agreement.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127147512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Calibration and self-test of RF transceivers","authors":"Yaning Zou, C. Munker, R. Stuhlberger, M. Valkama","doi":"10.1109/MWSCAS.2010.5548732","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548732","url":null,"abstract":"In the last few years cellular market well exceeded 1.3B cellular mobile devices shipped per year. The ongoing economic-driven shrink in technology towards nanoscale CMOS enables increased functionality in even smaller silicon area, however, technology effects including process variation, variability, temperature effects, flicker noise etc. put stringent challenges on the design and have significant impact on the production yield. Due to the huge volume yield, testing and Automated Test Equipment (ATE) have become a major cost factor in RF production. At the same time integration level and complexity of RF transceivers and SoCs have increased due to huge diversity of mobile communication standards ranging from 2G/3G to 4G, WLAN, BT, and GPS. RF devices are no longer purely RF devices. They integrate RF, analog and digital functions, all working together enabling the device to test and calibrate functions autonomously. This paper summarizes the key developments and trends in RF-BIST, with particular attention to improvements in testing and calibration of PLL loop-gain, second order modudulation, and I/Q impairments.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125120986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analog behavioral modeling of magnetoresistive sensors","authors":"H. Fardi, G. Alaghband","doi":"10.1109/MWSCAS.2010.5548883","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548883","url":null,"abstract":"A behavioral circuit model of anisotropic magneto resistance (AMR) sensors that operates by modulating the drive bias on soft-adjacent-layer is developed. The non-linear extrinsic behavior of the sensor is modeled by constructing a two-dimensional (2D) polynomial at DC level for the variation of the sensor drive current controlled by the self bias of the sensor and magnetic field bias. Analog Behavioral Model is used to implement the model in SPICE. The simulation of second harmonic (2f) sensitivity signal and its comparison to the experimental data in a bridge configuration is presented. The comparison made with the experimental data permits the accurate prediction of 2f measurement for AMR sensors.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125740340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new optimization technique for coefficient scaling in sigma-delta modulators","authors":"Etienne Collard-Fréchette, G. Gagnon","doi":"10.1109/MWSCAS.2010.5548820","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548820","url":null,"abstract":"This article proposes a new method for scaling the output swing of the integrators in a sigma-delta modulator. The algorithm takes in consideration the relative effect on the output signal-to-noise ratio of the thermal noise from each integrator to find a set of coefficients which implements the desired transfer functions while reducing the signal swing at each node. Simulation results show that the last two integrators output swing can be reduced by 50% and 90% respectively for a 0.5 dB signal-to-noise ratio reduction.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125939820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jun He, Chen Zhao, S. Lee, K. Peterson, R. Geiger, Degang Chen
{"title":"Highly linear very compact untrimmed on-chip temperature sensor with second and third order temperature compensation","authors":"Jun He, Chen Zhao, S. Lee, K. Peterson, R. Geiger, Degang Chen","doi":"10.1109/MWSCAS.2010.5548802","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548802","url":null,"abstract":"This paper proposes a CMOS structure as a highly linear on-chip temperature sensor. As long as all transistors are in saturation, the output of the structure is a VDD independent voltage source that linearly expresses CMOS threshold voltage, and hence is approximately linear in temperature. A new sizing strategy is introduced following a combined analytical and numerical optimization approach, which effectively removes both second and third order nonlinearities. Following this sizing approach, the sensor output voltage can be made very linear in temperature, with temperature INL (maximum temperature errors due to Vout temperature nonlinearity) within 0.05°C over the temperature range of −20~100°C. Results from corner simulations and Monte Carlo simulations demonstrate that the sensor linearity has excellent robustness over process variation and local device mismatches. With a standard two point calibration, the sensor's maximum output error can be confined within 0.15°C without any trimming. The sensor is very compact with a total active area around 200 µm2 when implemented in 0.18µm process.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123754987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Risk-sensitive optimal control for stochastic recurrent neural networks","authors":"Ziqian Liu, R. E. Torres, Miltiadis Kotinis","doi":"10.1109/MWSCAS.2010.5548858","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548858","url":null,"abstract":"As a continuation of our study, this paper extends our research results of optimality-oriented control from deterministic recurrent neural networks to stochastic recurrent neural networks, and presents a new theoretical design for the risk-sensitive optimal control of stochastic recurrent neural networks. The design procedure follows the technique of inverse optimality, and obtains risk-sensitive state feedback controllers that guarantee an achievable meaningful cost for a given risk-sensitivity parameter.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115200065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}