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2010 53rd IEEE International Midwest Symposium on Circuits and Systems最新文献

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A switched current sigma delta modulator using a low distortion feedfoward topology 采用低失真前馈拓扑结构的开关电流σ δ调制器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548808
C. Prior, C. Rodrigues
{"title":"A switched current sigma delta modulator using a low distortion feedfoward topology","authors":"C. Prior, C. Rodrigues","doi":"10.1109/MWSCAS.2010.5548808","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548808","url":null,"abstract":"Implementation of feedforward paths for low-distortion topologies on switched capacitor sigma-delta (SC-SD) modulators was successfully reported elsewhere [13]. In this paper we propose the use of a similar low distortion topology on an implementation of a switched current sigma-delta (SI-SD) modulator. The objective is a reduction of harmonic distortion observed in implementations with simple integrator cells. In this approach, one of the main SI cell drawbacks, the harmonic distortion due to conductance variation, can be reduced by alleviating the signal in the integrators path. In this approach, the integrators ideally process only noise. Relaxing requirements of integrators allows simpler and faster switched-current integrator circuits. The feedforward SI-SD modulator was designed in XFAB CMOS 0.6µm technology. Simulated results points to a reduction of harmonic distortion from 2% in a classical 2nd order feedback topology to 0.2% in the feed forward design. It also provides a reduction of 30% in the silicon area, and higher sampling frequency.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116124633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
How to do RF-BiST with virtually no extra circuits for RF-SoC products? 如何在RF-SoC产品几乎没有额外电路的情况下进行RF-BiST ?
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548735
D. Webster, Jerry Lopez, D. Lie
{"title":"How to do RF-BiST with virtually no extra circuits for RF-SoC products?","authors":"D. Webster, Jerry Lopez, D. Lie","doi":"10.1109/MWSCAS.2010.5548735","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548735","url":null,"abstract":"This paper describes novel RF Built-in Self Test (RFBiST) and RF Built-in-Self-Calibration (RF-BiSC) techniques that can test the performance of RF SoC's using on-chip resources as both test stimuli and response analyzers. Our RFBiST approach is to fully utilize existing on-chip circuitry to prevent adding extra die area, while remaining capable of performing various RF-SoC self-tests. Successful RF-BiST examples include internally measuring RF oscillators with onchip digital signals from an All-Digital Phase Locked Loop (ADPLL). Other RF-BiST examples cover various contributors to Error Vector Magnitude (EVM) such as gain, linearity, and phase noise. Functional RF-BiSTs, such as loop-back methods, can be verified from GSM/EDGE to WLAN SoCs through good correlation with comparable external tests. Additionally, RFBiST/ BiSC with on-chip digital controllers and compensation networks can help drastically reduce the cost of phase and amplitude calibration and the deployment time with improved uniformity for phased-array RADARs, benefiting both future military and commercial RADAR systems considerably.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122706405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
4.2K CMOS circuit design for digital readout of Single Electron Transistor electrometry 单电子晶体管电计数字读出的4.2K CMOS电路设计
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548666
K. Das, T. Lehmann, Md. Tanvir Rahman
{"title":"4.2K CMOS circuit design for digital readout of Single Electron Transistor electrometry","authors":"K. Das, T. Lehmann, Md. Tanvir Rahman","doi":"10.1109/MWSCAS.2010.5548666","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548666","url":null,"abstract":"We present the perspective of CMOS electronics as a candidate for the readout purposes of sensing devices such as the Single Electron Transistor (SET) at very low temperature. Fully Depleted Silicon on Insulator (FD-SOI) CMOS devices are less susceptible to low temperature anomalies compared to bulk devices. The electrical characteristics of a typical SET are too small in comparison to usual current/voltage levels for MOS circuits and thus imposes new complications in circuit design. We present a digital readout scheme of the SET best suited for scalable design. The circuit is implemented with commercial 0.5µm SOI CMOS process operating at 4.2K. The simulation results show successful detection of 200pA drain current of an SET biased at 10µV with 15µs detection speed and static power dissipation less than 45µW.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122506376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Performance analysis of CMOS Mode Locked class E Power Amplifier CMOS锁模E类功率放大器的性能分析
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548651
Pankaj Arora, J. Mukherjee, V. Agarwal
{"title":"Performance analysis of CMOS Mode Locked class E Power Amplifier","authors":"Pankaj Arora, J. Mukherjee, V. Agarwal","doi":"10.1109/MWSCAS.2010.5548651","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548651","url":null,"abstract":"The design of Class E Amplifiers is more difficult than other type of amplifiers as it is imposed by time domain constraints. This paper presents the performance analysis of Mode Locked class E Power Amplifiers using State Space Analysis Algorithm. A technique is introduced which is used to curb the negative effect of parasitic resistance of DC Feed Choke and the Power Amplifier operates at 2.4GHz and simulated with a 0.18µm CMOS process at a supply voltage of 2V.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"57 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114050891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power and area efficient 5T-SRAM with improved performance for low-power SoC in 65nm CMOS 功率和面积效率高的5T-SRAM，提高了65纳米CMOS低功耗SoC的性能
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548577
Hooman Jarollahi, R. Hobson
{"title":"Power and area efficient 5T-SRAM with improved performance for low-power SoC in 65nm CMOS","authors":"Hooman Jarollahi, R. Hobson","doi":"10.1109/MWSCAS.2010.5548577","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548577","url":null,"abstract":"This paper addresses performance and reliability issues in a 5T SRAM cell, and introduces a low power, reliable and high performance design in 65nm technology, which can be used as cache memory in processors and in low-power portable devices. The proposed SRAM cell features ∼13% area reduction compared to a typical 6T cell. In addition, it features a biasing ground line, VSSM, which is charged by channel leakage current from memory cells in standby, and is used to pre-charge a single bit-line and bias the negative supply voltage of each memory cell to suppress standby leakage power. A major standby power reduction is gained compared to conventional 5T and 6T designs and up to ∼30% compared to previous low-power 6T designs. The proposed design has read and static noises margins, as well as write ‘0’ and read performance that are comparable to typical 6T designs. Write ‘1’ is slower by ∼11–31% depending on design choices and can be improved with minor cost of area and power.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117283022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Leakage power considerations in actively running blocks 主动运行街区的漏电考虑
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548691
D. El-Dib
{"title":"Leakage power considerations in actively running blocks","authors":"D. El-Dib","doi":"10.1109/MWSCAS.2010.5548691","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548691","url":null,"abstract":"Leakage power reductions in active circuits have attracted researcher's attention for the last few years because of expectations of higher share of leakage power in total power consumption for downsized technologies. It was expected that leakage power will even overcome dynamic power consumption in submicron technologies. However, large portions of the research conducted for actively running processors has overseen two important factors of the design, the frequency of operation and the activity rate. It is shown that these must be investigated before starting to worry about leakage in actively running blocks. In fact, leakage energy constitutes less than 1% of total energy consumption in actively running parts.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129935364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A nuclear norm minimization approach to fractionally spaced blind channel equalization 分数间隔盲信道均衡的核范数最小化方法
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548703
K. Konishi, T. Furukawa
{"title":"A nuclear norm minimization approach to fractionally spaced blind channel equalization","authors":"K. Konishi, T. Furukawa","doi":"10.1109/MWSCAS.2010.5548703","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548703","url":null,"abstract":"This paper proposes an algorithm for the blind fractionally spaced equalization (FSE). We show that the rank minimization approach leads to reduce degrees of freedom in the blind FSE problem and improves the quality of equalization. By introducing the nuclear norm heuristic, the design problem of blind channel equalization is formulated as the nuclear norm minimization problem. We also show that the affection of noise is reduced by minimizing the nuclear norm. Numerical examples demonstrate the effectiveness of the proposed algorithm.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128798378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Current recycling in linear regulators for biomedical implants 生物医学植入物线性调节器的电流回收
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548750
Yuanyuan Yang, T. Lehmann
{"title":"Current recycling in linear regulators for biomedical implants","authors":"Yuanyuan Yang, T. Lehmann","doi":"10.1109/MWSCAS.2010.5548750","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548750","url":null,"abstract":"A novel current recycling dual linear regulating power supply is proposed in this paper. In systems, such as biomedical implants, requiring a high actuation supply voltage and a number of lower supply voltages generated by linear regulators, our technique allows the linear regulators to be stacked, effectively reducing the overall current consumption to that of a single regulator. We design a dual linear power supply in a 0.35µm high-voltage CMOS process and simulated results demonstrate a power saving in load of up to 49.4% compared with a conventional implementation.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129357532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 3–20 GHz SiGe HBT ultra-wideband LNA with gain and return loss control for multiband wireless applications 一种3-20 GHz SiGe HBT超宽带LNA，具有增益和回波损耗控制，适用于多频段无线应用
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548729
D. Howard, J. Poh, Tonmoy S. Mukerjee, J. Cressler
{"title":"A 3–20 GHz SiGe HBT ultra-wideband LNA with gain and return loss control for multiband wireless applications","authors":"D. Howard, J. Poh, Tonmoy S. Mukerjee, J. Cressler","doi":"10.1109/MWSCAS.2010.5548729","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548729","url":null,"abstract":"We present an ultra-wideband, Low Noise Amplifier (LNA) implemented in Silicon-Germanium Heterojunction Bipolar Transistor (SiGe HBT) technology. This SiGe LNA is broadband, covering the frequency range of 3–20 GHz, and achieves a peak gain of 21.3 dB. The SiGe LNA exhibits a Noise Figure (NF) of 4.2–5.2 dB across an 8–18 GHz band and consumes 35.2 mA from a 3.3 V supply.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124568896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Frequency divider design using the Λ-type negative-differential-resistance circuit 分频器设计采用Λ-type负差分电阻电路
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548795
Dong-Shong Liang, K. Gan, Kuan-Yu Chun
{"title":"Frequency divider design using the Λ-type negative-differential-resistance circuit","authors":"Dong-Shong Liang, K. Gan, Kuan-Yu Chun","doi":"10.1109/MWSCAS.2010.5548795","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548795","url":null,"abstract":"The behavior of a frequency divider circuit using a Λ-type negative differential resistance (NDR) circuit, which is composed of Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices, is studied. This frequency divider is mainly made of a MOS-HBT-NDR circuit, an inductor, and a capacitor. The operation is based on the long-period behavior of the NDR-based chaos circuit. We demonstrate the high-frequency consideration and characteristic of this frequency divider. The results show that the dividing ratio can be selected by modulating the input signal frequency.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126683823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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