Performance analysis of CMOS Mode Locked class E Power Amplifier

Abstract

The design of Class E Amplifiers is more difficult than other type of amplifiers as it is imposed by time domain constraints. This paper presents the performance analysis of Mode Locked class E Power Amplifiers using State Space Analysis Algorithm. A technique is introduced which is used to curb the negative effect of parasitic resistance of DC Feed Choke and the Power Amplifier operates at 2.4GHz and simulated with a 0.18µm CMOS process at a supply voltage of 2V.