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2010 53rd IEEE International Midwest Symposium on Circuits and Systems最新文献

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Sizing mixed-mode circuits by multi-objective evolutionary algorithms
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548688
I. Guerra-Gómez, E. Tlelo-Cuautle, Trent McConaghy, L. G. de la Fraga, G. Gielen, G. Reyes-Salgado, J. Muñoz-Pacheco
{"title":"Sizing mixed-mode circuits by multi-objective evolutionary algorithms","authors":"I. Guerra-Gómez, E. Tlelo-Cuautle, Trent McConaghy, L. G. de la Fraga, G. Gielen, G. Reyes-Salgado, J. Muñoz-Pacheco","doi":"10.1109/MWSCAS.2010.5548688","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548688","url":null,"abstract":"We show the behavior of the generations of two multi-objective evolutionary algorithms (MOEAs) for the optimal sizing of two mixed-mode circuits. The non-sorting genetic algorithm (NSGA-II), and the MOEA based on decomposition (MOEA/D) are used to size a second generation current conveyor (CCII+) and a current-feedback operational amplifier (CFOA). Both MOEAs take into account design constraints, and link HSPICE to evaluate the electrical characteristics of the CCII+ and CFOA. Differential evolution is used as genetic operator to show the behavior of the generations of the two MOEAs.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126887225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.18 µm CMOS integrated transimpedance amplifier-equalizer for 2.5 Gb/s 一个0.18µm CMOS集成的2.5 Gb/s的跨阻放大均衡器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548900
F. Aznar, S. Celma, B. Calvo, I. Lope
{"title":"A 0.18 µm CMOS integrated transimpedance amplifier-equalizer for 2.5 Gb/s","authors":"F. Aznar, S. Celma, B. Calvo, I. Lope","doi":"10.1109/MWSCAS.2010.5548900","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548900","url":null,"abstract":"This paper presents a transimpedance amplifier (TIA)-equalizer combination optical receiver for 2.5 Gbit/s communications realized in a standard 180 nm CMOS process. The first stage, a transimpedance amplifier (TIA), is based on a conventional structure with an inverting voltage amplifier and a feedback resistor, but incorporates a technique to prevent the TIA saturation at high input currents. Simulation results show an optical sensitivity of 4 µA for a BER = 10−12 and a maximum input current of 1.5 mApp, what leads to an input dynamic range above 52 dB. The TIA is followed by an equalizer which compensate the typical frequency response of an integrated photodiode. The power consumption is 6.5 mW for the TIA and 4.1 mW for the equalizer with 1.8 V supply.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130640057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low Distortion ΔΣ Modulator Employing modified charge-pump based switched-capacitor integrator 低失真ΔΣ调制器采用改进的电荷泵为基础的开关电容集成器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548655
Weilun Shen, Tao Wang, G. Temes
{"title":"Low Distortion ΔΣ Modulator Employing modified charge-pump based switched-capacitor integrator","authors":"Weilun Shen, Tao Wang, G. Temes","doi":"10.1109/MWSCAS.2010.5548655","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548655","url":null,"abstract":"Modified charge-pump based switched-capacitor integrator is a promising technique to reduce opamp power consumption. In this paper, design methodologies are introduced to incorporate such kind of integrator into a low-distortion delta-sigma modulator. A second-order delta-sigma modulator was designed and simulated to verify the proposed modulator topology.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"33 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of a 1-V 90-nm CMOS folded cascode LNA for multi-standard applications 针对多标准应用的1-V 90纳米CMOS折叠级联码LNA设计
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548704
E. Becerra-Alvarez, J. M. de la Rosa, Federico Sandoval
{"title":"Design of a 1-V 90-nm CMOS folded cascode LNA for multi-standard applications","authors":"E. Becerra-Alvarez, J. M. de la Rosa, Federico Sandoval","doi":"10.1109/MWSCAS.2010.5548704","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548704","url":null,"abstract":"This paper analyses the use of folded cascode Low Noise Amplifiers (LNAs) for the implementation of multi-standard wireless transceivers. The proposed LNA consists of a two-stage topology made up of a folded cascode and simple-stage amplifiers that use NMOS-varactor based tuning networks to make the operating frequency continuously programmable. The circuit has been designed and implemented in a 90-nm CMOS technology in order to cope with the requirements of GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b/g) standards. Practical design issues are analysed, considering the effect of circuit parasitics associated to both the chip package and integrated inductors, capacitors and varactors; as well as technology parameter deviations. The circuit design is optimized using genetic algorithms to achieve the required specifications with adaptive power consumption. Layout-extracted simulation results demonstrate a correct operation of the proposed circuit, showing a continuous tuning of Noise Figure (NF) and S-parameters within the 1.85–2.48GHz band, featuring NF<3.8dB, S21 >12dB and IIP3> −12dBm, with an adaptive power dissipation between 13.3mW and 23.1mW from a 1-V supply voltage.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123726105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A reconfigurable pattern matching hardware implementation using on-chip RAM-based FSM 使用片上基于ram的FSM的可重构模式匹配硬件实现
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548558
N. Rafla, Indrawati Gauba
{"title":"A reconfigurable pattern matching hardware implementation using on-chip RAM-based FSM","authors":"N. Rafla, Indrawati Gauba","doi":"10.1109/MWSCAS.2010.5548558","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548558","url":null,"abstract":"The use of synthesizable reconfigurable IP cores has increasingly become a trend in System on Chip (SoC) designs because of their flexibility and powerful functionality. The market introduction of multi-featured platform FPGAs equipped with embedded memory and processor blocks has further expanded the possibility of utilizing dynamic reconfiguration to improve overall system adaptability to meet varying product requirements. In this paper, a reconfigurable hardware implementation for pattern matching using Finite State machine (FSM) is proposed. The FSM design is RAM-based and is reconfigured on the fly through altering memory contents only. An embedded processor is used for orchestrating run time reconfiguration. Experimental results show that the system can reconfigure itself based on a new incoming pattern and perform the text search without the need of a host processor. Results also proved that each search iteration was executed in one clock cycle and the maximum achievable clock frequency is independent of search pattern length.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"93 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114101277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Leakage control in full adders with selectively stacked inverters 选择性堆叠逆变器的全加法器泄漏控制
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548678
S. Eratne, P. Nair, E. John
{"title":"Leakage control in full adders with selectively stacked inverters","authors":"S. Eratne, P. Nair, E. John","doi":"10.1109/MWSCAS.2010.5548678","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548678","url":null,"abstract":"Technology scaling beyond the 65nm regime has resulted in leakage power consumption emerging as a major design constraint. Several methods aiming at mitigating leakage power have been studied and tested. These include power-rail gating, input vector control, transistor body biasing, transistor stacking, etc. This paper extends the idea of transistor stacking but limiting it to the inverters in the given logic circuit or cell in order to obtain leakage savings. Stacking of inverters is effective in leakage current reduction during both the active and standby modes of the circuit. Stacking also has the advantage of not requiring any additional control circuitry. We examine the leakage power and delay variations for this approach and compare it with the method of power-rail gating. The results indicate that selective stacking of inverters can yield considerable leakage savings without causing significant delay penalties. Therefore it is suitable for cells such as full adders which are in the critical path of complex logic modules such as the microprocessor.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116268309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Second order approximation of the fractional laplacian operator for equal-ripple response 等纹响应的分数阶拉普拉斯算子的二阶近似
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548870
T. Freeborn, B. Maundy, A. Elwakil
{"title":"Second order approximation of the fractional laplacian operator for equal-ripple response","authors":"T. Freeborn, B. Maundy, A. Elwakil","doi":"10.1109/MWSCAS.2010.5548870","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548870","url":null,"abstract":"In this paper we propose a modification to a second order approximation of the fractional-order Laplacian operator, sα, where 0 < α < 1. We show how this proposed modification can be used to change the ripple error of both the magnitude and phase responses of the approximation when compared to the ideal case. Equal-ripple magnitude and phase responses that have both less cumulative error and less maximum ripple deviation are presented using this modification. A 1st order lowpass filter with fractional step of 0.8, that is of order 1.8, is implemented using the proposed approximation. Experimental results verify the operation of this approximation in the realization of the fractional step filter.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115910697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A latency-proof quantization noise reduction method for digitally-controlled ring oscillators 一种数字式环形振荡器的抗延迟量化降噪方法
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548570
Chengwen Liu, Rui He, X. Yu, W. Rhee, Zhihua Wang
{"title":"A latency-proof quantization noise reduction method for digitally-controlled ring oscillators","authors":"Chengwen Liu, Rui He, X. Yu, W. Rhee, Zhihua Wang","doi":"10.1109/MWSCAS.2010.5548570","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548570","url":null,"abstract":"This paper describes a quantization noise reduction method for ΔΣ based digitally-controlled ring oscillators (DCRO). A concept of the hybrid finite-impulse response (FIR) filter from the fractional-N PLL is extended to the DCRO design. Thanks to the parallel operation, the proposed filter based noise reduction method does not cause any additional latency to the digital PLL. Both behavioral and circuit-level simulations are performed, showing that out-of-band phase noise or short-term jitter caused by the ΔΣ modulator can be significantly reduced with the proposed method.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131956766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Charge reusing in switched-capacitor voltage multipliers with reduced dynamic losses 减少动态损耗的开关电容器电压乘法器中的电荷复用
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548869
Younis Allasasmeh, S. Gregori
{"title":"Charge reusing in switched-capacitor voltage multipliers with reduced dynamic losses","authors":"Younis Allasasmeh, S. Gregori","doi":"10.1109/MWSCAS.2010.5548869","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548869","url":null,"abstract":"In this work we study the application of charge reusing to switched-capacitor voltage multipliers. Considering three popular circuits (i.e. the Dickson, the heap, and the Fibonacci charge pumps), we analyze the dynamic power losses due to parasitic capacitances. We show how a charge reuse technique effectively decreases the dynamic power losses. The validity of our analysis is verified through simulations of design examples, which also illustrate the impact of charge reusing on voltage gain, output resistance, and conversion efficiency.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130023936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology 位式MTNCL:一种超低功耗位式流水线异步电路设计方法
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548680
Liang Zhou, S. Smith, J. Di
{"title":"Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology","authors":"Liang Zhou, S. Smith, J. Di","doi":"10.1109/MWSCAS.2010.5548680","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548680","url":null,"abstract":"This paper develops an ultra-low power design methodology for bit-wise pipelined asynchronous circuits, called bit-wise MTNCL, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. Compared to original NCL circuits implemented with all low-Vt and high-Vt transistors, respectively, it provides the leakage power advantages of the all high-Vt NCL implementation with a reasonable speed penalty compared to the all low-Vt design, requires less energy/operation, and has no area overhead.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134411729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
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