A 0.18 µm CMOS integrated transimpedance amplifier-equalizer for 2.5 Gb/s

Abstract

This paper presents a transimpedance amplifier (TIA)-equalizer combination optical receiver for 2.5 Gbit/s communications realized in a standard 180 nm CMOS process. The first stage, a transimpedance amplifier (TIA), is based on a conventional structure with an inverting voltage amplifier and a feedback resistor, but incorporates a technique to prevent the TIA saturation at high input currents. Simulation results show an optical sensitivity of 4 µA for a BER = 10−12 and a maximum input current of 1.5 mApp, what leads to an input dynamic range above 52 dB. The TIA is followed by an equalizer which compensate the typical frequency response of an integrated photodiode. The power consumption is 6.5 mW for the TIA and 4.1 mW for the equalizer with 1.8 V supply.