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2010 53rd IEEE International Midwest Symposium on Circuits and Systems最新文献

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Energy efficient Digital Signal Processing 节能数字信号处理
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548827
N. Magotra, J. Larimer
{"title":"Energy efficient Digital Signal Processing","authors":"N. Magotra, J. Larimer","doi":"10.1109/MWSCAS.2010.5548827","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548827","url":null,"abstract":"This paper focuses on issues related to energy efficient Digital Signal Processing (DSP) - taking a Systems-to-Silicon approach. This implies that achieving maximum energy efficiency in a DSP system is a distributed task from the systems level (compilers, algorithm design etc.) to a silicon (transistor, process technologies etc.) level. It addresses how we view this problem and also uses specific application areas such as hearing devices and medical imaging to illustrate the needs and concepts involved in this context.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"11 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134320970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A power effective 5-bit 600 MS/s binary-search ADC with simplified switching 具有简化开关的高效5位600 MS/s二值搜索ADC
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548553
S. Wong, U. Chio, Hou-Lon Choi, Chi-Hang Chan, Sai-Weng Sin, S. U, R. Martins
{"title":"A power effective 5-bit 600 MS/s binary-search ADC with simplified switching","authors":"S. Wong, U. Chio, Hou-Lon Choi, Chi-Hang Chan, Sai-Weng Sin, S. U, R. Martins","doi":"10.1109/MWSCAS.2010.5548553","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548553","url":null,"abstract":"This paper proposes the design of a binary search ADC that uses two different techniques, namely, distributed-residue and folding. These can prevent signal dependent offset and reduce the switching network complexity. A 5-bit binary-search ADC applying such proposed techniques has been developed in 65 nm CMOS. It consumes 540 µW under 1V supply voltage at the operating frequency of 600 MS/s. The simulation results demonstrate that the design achieves a SNDR of 30.8 dB at Nyquist input frequency with a figure of merit (FOM) of 32 fJ/conversion-step.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130870144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A high efficiency current-mode DC-DC step-down converter with wide range of output current 一种输出电流范围宽的高效率电流型DC-DC降压变换器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548810
Chia-Min Chen, Kai-Hsiu Hsu, C. Hung
{"title":"A high efficiency current-mode DC-DC step-down converter with wide range of output current","authors":"Chia-Min Chen, Kai-Hsiu Hsu, C. Hung","doi":"10.1109/MWSCAS.2010.5548810","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548810","url":null,"abstract":"This paper presents a high efficiency current-mode DC-DC step-down converter with wide range of output current. The converter adaptively operates as Pulse-Width Modulation (PWM). An on-chip current sensing technique is employed to reduce external components and no extra I/O pins are needed for the current-mode controller. A soft-start operation is designed to eliminate the excess large current during the startup of the regulator. The circuit has been designed with TSMC 2P4M 0.35 µm CMOS process. The range of the supply voltage is from 2 to 5V, which is suitable for single-cell lithium-ion battery.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131123039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new multiphase interleaving buck converter with bypass cell capacitor and inductor 一种新型带旁路电容和电感的多相交错降压变换器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548812
T. Taufik, R. Prasetyo, D. Dolan, D. Garinto
{"title":"A new multiphase interleaving buck converter with bypass cell capacitor and inductor","authors":"T. Taufik, R. Prasetyo, D. Dolan, D. Garinto","doi":"10.1109/MWSCAS.2010.5548812","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548812","url":null,"abstract":"As the number of transistors in microprocessors increases per Moore's Law, their power requirement increases accordingly. This poses design challenges for their power supply module especially when they operate at sub voltage range. This paper presents a new multiphase topology that addresses these challenges. Laboratory tests on a hardware prototype of the topology shows improved load regulation, output voltage ripple and dynamic response time compared to a commercially available power supply module.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133559918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
LUT-based circuits for future wireless systems 未来无线系统的基于lut的电路
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548722
P. Meher
{"title":"LUT-based circuits for future wireless systems","authors":"P. Meher","doi":"10.1109/MWSCAS.2010.5548722","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548722","url":null,"abstract":"The future wireless systems have three mutually conflicting demands, e.g., high computational-bandwith, low-power consumption and reconfigurability. Such a set of demands will continue to be a challenge to the designers of computing circuits and systems for the next generation wireless communication. The lookup-table (LUT)-based arithmetic circuits have significant potential to satisfy these requirements to a great extent. In this paper, we give a brief overview of the odd-multiple storage (OMS) scheme and antisymmetric product coding (APC) approach for optimized implementation of LUT-based multiplication, and present a generalized version of APC for high-speed and high-precision multiplication.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133448244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Self-regulating sensor network 自调节传感器网络
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548584
F. Mili, J. Meyer
{"title":"Self-regulating sensor network","authors":"F. Mili, J. Meyer","doi":"10.1109/MWSCAS.2010.5548584","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548584","url":null,"abstract":"Power is a critical resource in sensor networks, especially when the nodes are un-tethered and used in long running applications. Many approaches have been developed to exploit the inherent space and time redundancy in the data collected by sensor networks by using selective querying. In selective querying, at any given time, only a percentage of the nodes is queried; the rest are put in sleep mode. The key feature of selective querying is the method by which it decides which nodes are active and which nodes are sleep at every time period. The published literature catalogs a rich variety of selection criteria, yet, it barely addresses the orthogonal problem: what percentage of the nodes should be active. In this paper we describe algorithms we have used to make the sensor network self-regulate, i.e. the network continuously monitors the level of activity in the environment and regulates the level of activity of the network accordingly. We further use the analogy of natural self-regulation by also gauging the level of activity to the amount and distribution of resources available.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133662921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Ultra low-voltage Delay Locked Loop using carbon nanotubes 采用碳纳米管的超低电压延时锁相环
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548708
J. Ajit, Yong-Bin Kim
{"title":"Ultra low-voltage Delay Locked Loop using carbon nanotubes","authors":"J. Ajit, Yong-Bin Kim","doi":"10.1109/MWSCAS.2010.5548708","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548708","url":null,"abstract":"Carbon Nanotube FET technology is investigated to implement ultra low-voltage DLL and simulation results show that operation at supply voltage as low as 0.3 V is possible with a peak jitter of 13 ps and lock is acquired in 7 cycles with a clock frequency range from 330 MHz to 10 GHz. The characteristics is dependent on the nanotube parameters and the optimum nanotube diameter is found to be 1.35 nm.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115549266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On Tunable Compact Analog Circuits with Nanoscale DG-MOSFETs 纳米级dg - mosfet可调谐紧凑模拟电路研究
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548647
S. Kaya, H. Hamed
{"title":"On Tunable Compact Analog Circuits with Nanoscale DG-MOSFETs","authors":"S. Kaya, H. Hamed","doi":"10.1109/MWSCAS.2010.5548647","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548647","url":null,"abstract":"DG-MOSFETs, ideally suited for digital applications below 50nm, can be effectively used also for analog circuits, especially in independent drive (IDDG) configuration. As MOSFETs with two closely coupled channels, they can locally and dynamically alter the front gate threshold by an applied back-gate bias, thus enabling tunability. We explore how the IDDG-MOSFETs could be deployed as creative tools to conveniently tune the response of conventional CMOS analog circuits such as current mirrors, integrators, operational transconductance amplifiers and high-order filters. We illustrate the design of such tunable circuits and analyze their performance using TCAD simulations. The topologies and biasing schemes explored here show how the nanoscale IDDG-MOSFETs can have a big impact on the realization of efficient and compact circuits commonly used in low-power and wireless communication systems.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114685625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GPU accelerated elliptic curve cryptography in GF(2m) GF(2m)中的GPU加速椭圆曲线密码
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548560
A. E. Cohen, K. Parhi
{"title":"GPU accelerated elliptic curve cryptography in GF(2m)","authors":"A. E. Cohen, K. Parhi","doi":"10.1109/MWSCAS.2010.5548560","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548560","url":null,"abstract":"This paper presents the Graphics Processing Unit (GPU) accelerated version of the LSB Invariant scalar point multiplication for binary elliptic curves. This method was implemented using the CUDA programming language for nVidia graphics cards. With a parallel factor of (length+1) and López-Dahab projective coordinate P<inf>i</inf>'s, on an nVidia GTX 285 graphics card precomputation takes 190.203995 ms while the actual scalar point multiplication takes 173.121002 ms for GF(2<sup>163</sup>). With a parallel factor of (length+1)*(length) and López-Dahab projective coordinate P<inf>i</inf>'s, on an nVidia GTX 285 graphics card precomputation of 2<sup>i</sup>P points takes 9.545 ms while the actual scalar point multiplication takes 10.743 ms (∼93.0839 kP/s) for GF(2<sup>163</sup>). With a parallel factor of (length+1)*(length) and affine coordinate P<inf>i</inf>'s, on an nVidia GTX 285 graphics card precomputation takes 140.078003 ms for GF(2<sup>163</sup>) while the actual scalar point multiplication takes 10.363000 ms (∼96.4972 kP/s) for GF(2<sup>163</sup>).","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114902100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Systolic-array architecture for 2D IIR Wideband dual-beam space-time plane-wave filters 二维IIR宽带双波束空时平面波滤波器的收缩阵列结构
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548677
C. Wijenayake, A. Madanayake, L. Bruton
{"title":"Systolic-array architecture for 2D IIR Wideband dual-beam space-time plane-wave filters","authors":"C. Wijenayake, A. Madanayake, L. Bruton","doi":"10.1109/MWSCAS.2010.5548677","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548677","url":null,"abstract":"A spatio-temporal 2D IIR broadband plane-wave filter having 2 user-selectable passbands is proposed using the concept of 2D network resonance. The plane-wave filter is capable of the highly-selective directional enhancement of 2 far-field plane-waves in the presence of undesired waves at different directions of arrival. A massively-parallel systolic-array processor architecture is proposed for the real-time VLSI implementation of the filter. The architecture is designed, simulated, and implemented as a prototype clocked at 50 MHz, using a Xilinx Virtex-4 Sx35-10ff668 FPGA device. The proposed systolic-array delivers a real-time throughput of one-frame-per-clock-cycle (OPFCC) which implies 50 million linear frames per second. The design is simulated (for a 32 element array) and tested on-chip (for an 18-element array) using 2D impulse- and frequency-responses, and using multi-directional broadband plane-wave test sequences.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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