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2010 53rd IEEE International Midwest Symposium on Circuits and Systems最新文献

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Fast arithmetic error feedback circuits for digital filters with shift operation circuits and shared multiplier 带移位运算电路和共享乘法器的数字滤波器的快速算术误差反馈电路
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548749
M. Nakamoto, T. Hinamoto, S. Ohno
{"title":"Fast arithmetic error feedback circuits for digital filters with shift operation circuits and shared multiplier","authors":"M. Nakamoto, T. Hinamoto, S. Ohno","doi":"10.1109/MWSCAS.2010.5548749","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548749","url":null,"abstract":"In this paper, we propose a fast arithmetic error feedback (EF) structure with shift operation circuits and shared multiplier. For optimization of EF network, we show the design method based on the Lagrange multiplier method for designing the shared multiplier and the branch and bound based algorithm for optimization of the shift operation circuits. The branch and bound method can reduce the calculation cost because the sub-trees can be cut based on the lower bound estimation. Finally, we present a numerical example by designing the EF with shift operation circuits and shared multiplier. From the results, we demonstrate the effectiveness of the proposed method and show the calculation time is a few seconds.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of continuous time filters by delay line adjustment 延迟线调整法优化连续时间滤波器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548770
D. Bruckmann, Karsten Konrad
{"title":"Optimization of continuous time filters by delay line adjustment","authors":"D. Bruckmann, Karsten Konrad","doi":"10.1109/MWSCAS.2010.5548770","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548770","url":null,"abstract":"Digital signal processing in continuous-time can result in a number of advantages compared to classical sampled data systems, while the inherent advantages of digital implementations with respect to programmability and noise immunity are retained. A main difference to sampled data systems is the realization of the delay elements which are implemented as quasi-continuous time delay lines. In this paper it will be shown, that an additional degree of freedom is thus given, since the filter characteristic depends on the length of the delay lines. It will be shown, that an optimization of the filter characteristic can be performed by adjusting the delay lines. This will be demonstrated for filter structures well-suited for continuous time realization.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116293966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1.8-V 6.5-GHz low power wide band single-phase clock CMOS 2/3 prescaler 一种1.8 v 6.5 ghz低功耗宽带单相时钟CMOS 2/3预分频器
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548580
M. Krishna, M. Do, C. Boon, K. Yeo, W. M. Lim
{"title":"A 1.8-V 6.5-GHz low power wide band single-phase clock CMOS 2/3 prescaler","authors":"M. Krishna, M. Do, C. Boon, K. Yeo, W. M. Lim","doi":"10.1109/MWSCAS.2010.5548580","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548580","url":null,"abstract":"In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed ⅔ prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit power of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-⅔ unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116436284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A memristor SPICE model for designing memristor circuits 用于设计忆阻电路的忆阻SPICE模型
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548803
M. Mahvash, A. C. Parker
{"title":"A memristor SPICE model for designing memristor circuits","authors":"M. Mahvash, A. C. Parker","doi":"10.1109/MWSCAS.2010.5548803","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548803","url":null,"abstract":"The memristor, a circuit element, was first presented by Leon Chua in 1971. The physical implementation of the memristor was created by scientists at HP Labs in 2008 and the coupled variable resistor model was proposed. Here we show a SPICE model for such a memristor using dependent voltage sources. The model is validated by simulating simple circuits and comparing with the expected results. The proposed model makes it possible to design and simulate memristor circuits using SPICE. We simulate two circuits, a low pass filter in which a memristor is in series with a resistor and an integrator circuit with operational amplifier. The results are compared with inductor circuits in which a memristor is replaced by an inductor. The comparison shows that a memristor is acting like an inductor under certain conditions. Since the memristor has great performance in terms of power dissipation and with its nanometer size there might be a possible application of the memristor to be used as an inductor.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123674282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 88
MEMS acoustic array embedded in an FPGA based data acquisition and signal processing system 基于FPGA的嵌入式MEMS声阵列数据采集与信号处理系统
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548866
M. Turqueti, J. Saniie, E. Oruklu
{"title":"MEMS acoustic array embedded in an FPGA based data acquisition and signal processing system","authors":"M. Turqueti, J. Saniie, E. Oruklu","doi":"10.1109/MWSCAS.2010.5548866","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548866","url":null,"abstract":"Acoustic arrays are currently utilized in many different applications, ranging from consumer electronics to military systems. Active research on sensors, hardware, algorithms, and system integration specific to acoustic arrays are ongoing on a wide range of engineering fields. Applications such as sound source separation, sound navigation, sound imaging, and speech recognition are few of the many possible applications that benefit acoustic sensor array. Using multiple sensors in arrays has many advantages; however it is also more challenging. As the number of signals increases, the complexity of the electronics to acquire and process the data will grow as well. Such challenge can be quite formidable depending on the number of sensors, processing speed, and complexity of the target application. This paper describes the design and implementation of a 52 microphone MEMS array, embedded in an FPGA platform with real-time processing capabilities. The paper also provides the first results on the use of acoustic array as a source separation system utilizing Independent Component Analysis (ICA) technique.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124707218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A system architecture for automated charge modification of analog memories 模拟存储器的自动电荷修改系统架构
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548833
Hector X. Roman, G. Serrano
{"title":"A system architecture for automated charge modification of analog memories","authors":"Hector X. Roman, G. Serrano","doi":"10.1109/MWSCAS.2010.5548833","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548833","url":null,"abstract":"This paper describes a system architecture for automated charge modification of analog memories. The proposed circuit uses a constant charge injection scheme along with a negative feedback loop to allow automated on-chip programming of floating-gate transistors to a desired target value. In addition, array programming of analog memories is enabled with a parameter independent target voltage generator circuit. Feasibility of the proposed approach is demonstrated with experimental results from a 0.5µm CMOS process prototype IC. Results for onchip programming of a single device and automated programming of an array of memories are presented.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128328411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Optimization of PCB via design considering its physical length parameters 考虑PCB物理长度参数的设计优化
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548778
A. Zenteno, David Reina, G. Regalado
{"title":"Optimization of PCB via design considering its physical length parameters","authors":"A. Zenteno, David Reina, G. Regalado","doi":"10.1109/MWSCAS.2010.5548778","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548778","url":null,"abstract":"This paper presents an investigation in the design of signal vias in multilayered printed circuit boards (PCB) technology, from a signal integrity point of view, for high-speed applications such as processors' validation platforms. Vias have been designed according with technological design capabilities. Different physical aspect ratios have been considered in the analysis, and then numerical results are compared with S-parameter. Also, time-domain reflectometry (TDR) simulations on representative test structures are analyzed in order to minimize the via discontinuity effect.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128365728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A framework for automatic CMOS OpAmp sizing 一种CMOS OpAmp自动定径的框架
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548899
Praveen K. Meduri, S. Dhali
{"title":"A framework for automatic CMOS OpAmp sizing","authors":"Praveen K. Meduri, S. Dhali","doi":"10.1109/MWSCAS.2010.5548899","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548899","url":null,"abstract":"The problem of automatic CMOS OpAmp sizing is addressed. Given the specifications and the netlist of the OpAmp, our approach produces a design that has the accuracy of the BSIM models used for simulation and the advantage of a quick design time. The approach is based on generating an initial first-order design by using geometric programming and then refining it using simulations. Device-level simulations performed on a two stage OpAmp prove the efficacy of our approach.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128739983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analysis of topology considerations in indoor ZigBee meshed networks 室内ZigBee网状网络拓扑考虑因素分析
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548841
V. Torres, J. Becerra, F. Esparza, A. Lopez, F. Falcone
{"title":"Analysis of topology considerations in indoor ZigBee meshed networks","authors":"V. Torres, J. Becerra, F. Esparza, A. Lopez, F. Falcone","doi":"10.1109/MWSCAS.2010.5548841","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548841","url":null,"abstract":"In this paper, system simulation for indoor meshed ZigBee networks is presented. The behavior of the radio channel is evaluated by means of 3D ray tracing algorithms that has been developed in order to analyze interference in a scenario of coexistence of two ZigBee meshed networks which are adjacent one to the other in a particular indoor case. Due to the influence of the indoor environment, topological considerations are relevant in the overall evaluation of the meshed networks. The results aid in modeling the behavior ZigBee systems in arbitrary indoor environments, as well as in adequate planning of large sensor networks based on ZigBee.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129657903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An edge-list compression scheme for 2-D graphic system 二维图形系统的边表压缩方案
2010 53rd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2010-08-16 DOI: 10.1109/MWSCAS.2010.5548742
Yun-Nan Chang, Ting-Chi Tong
{"title":"An edge-list compression scheme for 2-D graphic system","authors":"Yun-Nan Chang, Ting-Chi Tong","doi":"10.1109/MWSCAS.2010.5548742","DOIUrl":"https://doi.org/10.1109/MWSCAS.2010.5548742","url":null,"abstract":"This paper presents an edge-list compression scheme for the two-dimensional (2D) graphic systems. To fill a 2D graphic object described by complex curve paths, either enormous global edge-table has to be created, or a more economic line-based edge-list can be utilized. The latter approach, however, will sacrifice the rendering quality by approximating the curve using straight-lines. Therefore, this paper proposes a new edge-list structure, which first divides each path of the object into several upward and downward segments. Each segment will then be coded based on the difference vector of neighboring pixels, and the quadrant this vector belongs to. The entire path can be converted into a compact bit-stream. To decode the bit-stream, an additional link-list structure has to be built, which contains the direct access links to the entry points in the bit-stream in order to fetch the local lowest points to produce an active edge-list for each scan line. Our preliminary results show that the proposed scheme can reduce the overall edge-table size by an average factor of 15.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122359030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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