{"title":"一种1.8 v 6.5 ghz低功耗宽带单相时钟CMOS 2/3预分频器","authors":"M. Krishna, M. Do, C. Boon, K. Yeo, W. M. Lim","doi":"10.1109/MWSCAS.2010.5548580","DOIUrl":null,"url":null,"abstract":"In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed ⅔ prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit power of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-⅔ unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"A 1.8-V 6.5-GHz low power wide band single-phase clock CMOS 2/3 prescaler\",\"authors\":\"M. Krishna, M. Do, C. Boon, K. Yeo, W. M. Lim\",\"doi\":\"10.1109/MWSCAS.2010.5548580\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed ⅔ prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit power of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-⅔ unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively.\",\"PeriodicalId\":245322,\"journal\":{\"name\":\"2010 53rd IEEE International Midwest Symposium on Circuits and Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-08-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 53rd IEEE International Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2010.5548580\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2010.5548580","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.8-V 6.5-GHz low power wide band single-phase clock CMOS 2/3 prescaler
In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed ⅔ prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit power of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-⅔ unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively.