一种1.8 v 6.5 ghz低功耗宽带单相时钟CMOS 2/3预分频器

M. Krishna, M. Do, C. Boon, K. Yeo, W. M. Lim
{"title":"一种1.8 v 6.5 ghz低功耗宽带单相时钟CMOS 2/3预分频器","authors":"M. Krishna, M. Do, C. Boon, K. Yeo, W. M. Lim","doi":"10.1109/MWSCAS.2010.5548580","DOIUrl":null,"url":null,"abstract":"In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed ⅔ prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit power of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-⅔ unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"A 1.8-V 6.5-GHz low power wide band single-phase clock CMOS 2/3 prescaler\",\"authors\":\"M. Krishna, M. Do, C. Boon, K. Yeo, W. M. Lim\",\"doi\":\"10.1109/MWSCAS.2010.5548580\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed ⅔ prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit power of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-⅔ unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively.\",\"PeriodicalId\":245322,\"journal\":{\"name\":\"2010 53rd IEEE International Midwest Symposium on Circuits and Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-08-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 53rd IEEE International Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2010.5548580\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2010.5548580","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26

摘要

本文研究了基于/ - 2 / 3预分频器的扩展型真单相时钟(E-TSPC)的开关和短路功耗以及工作频率。基于此分析,我们提出并实现了一种新的超低功耗宽带前置滤波器,该滤波器采用GlobalFoundries 0.18µm CMOS技术。与现有的E-TSPC架构相比,本文提出的三分之二预分频器工作频率可达6.5 GHz,消除了除2运算期间第一个D触发器(DFF)的开关和短路功率,也消除了第二个D触发器第一级的短路功耗。与1.8 v电源电压下的相同技术相比,在除以2操作期间,总功耗降低了50%。建议的除以-⅔单位在除以2和除以3模式下分别消耗1 mW和1.8 mW的功率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 1.8-V 6.5-GHz low power wide band single-phase clock CMOS 2/3 prescaler
In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed ⅔ prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit power of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-⅔ unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信