{"title":"采用碳纳米管的超低电压延时锁相环","authors":"J. Ajit, Yong-Bin Kim","doi":"10.1109/MWSCAS.2010.5548708","DOIUrl":null,"url":null,"abstract":"Carbon Nanotube FET technology is investigated to implement ultra low-voltage DLL and simulation results show that operation at supply voltage as low as 0.3 V is possible with a peak jitter of 13 ps and lock is acquired in 7 cycles with a clock frequency range from 330 MHz to 10 GHz. The characteristics is dependent on the nanotube parameters and the optimum nanotube diameter is found to be 1.35 nm.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"182 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Ultra low-voltage Delay Locked Loop using carbon nanotubes\",\"authors\":\"J. Ajit, Yong-Bin Kim\",\"doi\":\"10.1109/MWSCAS.2010.5548708\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Carbon Nanotube FET technology is investigated to implement ultra low-voltage DLL and simulation results show that operation at supply voltage as low as 0.3 V is possible with a peak jitter of 13 ps and lock is acquired in 7 cycles with a clock frequency range from 330 MHz to 10 GHz. The characteristics is dependent on the nanotube parameters and the optimum nanotube diameter is found to be 1.35 nm.\",\"PeriodicalId\":245322,\"journal\":{\"name\":\"2010 53rd IEEE International Midwest Symposium on Circuits and Systems\",\"volume\":\"182 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-08-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 53rd IEEE International Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2010.5548708\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2010.5548708","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Ultra low-voltage Delay Locked Loop using carbon nanotubes
Carbon Nanotube FET technology is investigated to implement ultra low-voltage DLL and simulation results show that operation at supply voltage as low as 0.3 V is possible with a peak jitter of 13 ps and lock is acquired in 7 cycles with a clock frequency range from 330 MHz to 10 GHz. The characteristics is dependent on the nanotube parameters and the optimum nanotube diameter is found to be 1.35 nm.
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