Ultra low-voltage Delay Locked Loop using carbon nanotubes

Abstract

Carbon Nanotube FET technology is investigated to implement ultra low-voltage DLL and simulation results show that operation at supply voltage as low as 0.3 V is possible with a peak jitter of 13 ps and lock is acquired in 7 cycles with a clock frequency range from 330 MHz to 10 GHz. The characteristics is dependent on the nanotube parameters and the optimum nanotube diameter is found to be 1.35 nm.