Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology

Abstract

This paper develops an ultra-low power design methodology for bit-wise pipelined asynchronous circuits, called bit-wise MTNCL, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. Compared to original NCL circuits implemented with all low-Vt and high-Vt transistors, respectively, it provides the leakage power advantages of the all high-Vt NCL implementation with a reasonable speed penalty compared to the all low-Vt design, requires less energy/operation, and has no area overhead.