Modified Elmore delay model for VLSI interconnect

Abstract

This paper describes a simple method of calculating delay of an RC ladder which is often encountered in VLSI interconnect analysis. The method first deals with a specific case where R and C are identical and the transfer function in closed form, is derived for arbitrary number of stages. The roots of the transfer function is then found in closed form and from there exact delay calculation is made. For arbitrary RC values, the derived method is combined with Elmore delay and a modified simple delay metric is proposed. For a first order approximation, the proposed method is matched with Elmore model and results are found more accurate at same computational requirement.