High resolution low power 0.6µm CMOS 40MHz dynamic latch comparator

Abstract

In order to diminish circuit complexity and power dissipation, the simple configuration of the dynamic latch comparator is revisited. This paper proposes and analyzes a comparator that consists of a preamplifier using negative resistance as a load and a double regenerative dynamic latch. A discussion of the dynamic latch is presented and the effect of transistor sizes in the time constant and the offset voltage is explained briefly. The comparator is designed in a 0.6µm CMOS technology. Monte Carlo simulation using Virtuoso® Spectre shows that the comparator has a resolution of 1.8mV and dissipates 750µW of power when working at 40MHz.