{"title":"一种低功率线性比无关的DAC，应用于多位ΔΣ adc","authors":"Yu Song, Zhe Gao, Z. Ignjatovic","doi":"10.1109/MWSCAS.2010.5548734","DOIUrl":null,"url":null,"abstract":"A low power linearity-ratio-independent DAC for ΔΣ data converters is proposed in this paper. By using a gainboosted sub-threshold inverter as an amplifier, circuit power consumption is decreased significantly. The sensitivity of the differential DAC output linearity on circuit mismatches is reduced by using mutually-referred inputs. In a 0.13um CMOS technology, Monte-Carlo analysis and transistor-level simulations show that with 660µW power consumption, the DAC demonstrates 16 bit linearity at an 8MHz output rate. Its differential output swing is about 1.2V with a 1.2V power supply. A multi-bit ΔΣ modulator is designed using the proposed DAC.","PeriodicalId":245322,"journal":{"name":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A low power linearity-ratio-independent DAC with application in multi-bit ΔΣ ADCs\",\"authors\":\"Yu Song, Zhe Gao, Z. Ignjatovic\",\"doi\":\"10.1109/MWSCAS.2010.5548734\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low power linearity-ratio-independent DAC for ΔΣ data converters is proposed in this paper. By using a gainboosted sub-threshold inverter as an amplifier, circuit power consumption is decreased significantly. The sensitivity of the differential DAC output linearity on circuit mismatches is reduced by using mutually-referred inputs. In a 0.13um CMOS technology, Monte-Carlo analysis and transistor-level simulations show that with 660µW power consumption, the DAC demonstrates 16 bit linearity at an 8MHz output rate. Its differential output swing is about 1.2V with a 1.2V power supply. A multi-bit ΔΣ modulator is designed using the proposed DAC.\",\"PeriodicalId\":245322,\"journal\":{\"name\":\"2010 53rd IEEE International Midwest Symposium on Circuits and Systems\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-08-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 53rd IEEE International Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2010.5548734\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 53rd IEEE International Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2010.5548734","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low power linearity-ratio-independent DAC with application in multi-bit ΔΣ ADCs
A low power linearity-ratio-independent DAC for ΔΣ data converters is proposed in this paper. By using a gainboosted sub-threshold inverter as an amplifier, circuit power consumption is decreased significantly. The sensitivity of the differential DAC output linearity on circuit mismatches is reduced by using mutually-referred inputs. In a 0.13um CMOS technology, Monte-Carlo analysis and transistor-level simulations show that with 660µW power consumption, the DAC demonstrates 16 bit linearity at an 8MHz output rate. Its differential output swing is about 1.2V with a 1.2V power supply. A multi-bit ΔΣ modulator is designed using the proposed DAC.
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