A low power linearity-ratio-independent DAC with application in multi-bit ΔΣ ADCs

Abstract

A low power linearity-ratio-independent DAC for ΔΣ data converters is proposed in this paper. By using a gainboosted sub-threshold inverter as an amplifier, circuit power consumption is decreased significantly. The sensitivity of the differential DAC output linearity on circuit mismatches is reduced by using mutually-referred inputs. In a 0.13um CMOS technology, Monte-Carlo analysis and transistor-level simulations show that with 660µW power consumption, the DAC demonstrates 16 bit linearity at an 8MHz output rate. Its differential output swing is about 1.2V with a 1.2V power supply. A multi-bit ΔΣ modulator is designed using the proposed DAC.