2023 IEEE International 3D Systems Integration Conference (3DIC)最新文献

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs 使用细间距混合键合和tsv的3晶片堆叠3d - ic的设计实现

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10155075

M. Naeim, Hanqi Yang, Pinhong Chen, Rong Bao, Antoine Dekeyser, G. Sisto, Moritz Brunion, Rongmei Chen, G. V. D. Plas, E. Beyne, D. Milojevic

引用次数: 0

A Study on a Tether-Less Approach Towards Micro-Transfer-Printing of Large-Footprint Power Micro-Inductor Chiplets 大尺寸功率微电感芯片微转移打印的无系绳方法研究

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10155034

Somnath Pal, Liang Ye, J. O'Callaghan, F. Atar, C. O'Mathúna, B. Corbett, R. Sai, Sambuddha Khan

{"title":"A Study on a Tether-Less Approach Towards Micro-Transfer-Printing of Large-Footprint Power Micro-Inductor Chiplets","authors":"Somnath Pal, Liang Ye, J. O'Callaghan, F. Atar, C. O'Mathúna, B. Corbett, R. Sai, Sambuddha Khan","doi":"10.1109/3DIC57175.2023.10155034","DOIUrl":"https://doi.org/10.1109/3DIC57175.2023.10155034","url":null,"abstract":"In recent years, need for large-scale, multi-layer, high-capacity integration for electronic systems has sky-rocketed. In this regard, a novel heterogeneous integration technique called Micro-transfer-printing $(mu mathbf{TP})$ has attracted a lot of attention due to its unique ability to integrate chiplets from heterogeneous sources on to a target substrate. Typically, the chiplets are picked up from a donor substrate using an elastomer stamp by breaking the surrounding micro-tethers and then printed onto a target substrate for further processing. Despite its success in applications like sensors, photovoltaics, photonics, etc., $mu mathbf{TP}$ finds its limitation in handling chiplet dimensions larger than 100 $mathbf{x} 100 mathrm{x} 20 mu mathbf{m}^{3}$. Therefore, reports on $mu mathbf{TP}$ of passive components like micro-inductors and micro-transformers with dimension in mm x mm and thickness of 100s of $mu mathbf{m}$ are non-existent. In this paper, a completely novel, non-classical, tether-less approach has been demonstrated for micro-inductors with large footprint. This paper also reports a customized PDMS stamp fabrication and optimized post-fabrication sample preparation steps, such as, substrate thinning and polishing while retaining device performance intact.","PeriodicalId":245299,"journal":{"name":"2023 IEEE International 3D Systems Integration Conference (3DIC)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115639384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last 超长间距PVD对TSV金属化及基于Via-last的模到晶圆3D集成的影响

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10154930

Jiaying Shen, Chang Liu, Tadaaki Hoshi, Atsushi Sinoda, H. Kino, Tetsu Tanaka, M. Mariappan, M. Koyanagi, T. Fukushima

引用次数: 0

Measurement Point Selection Algorithms for Testing Power TSVs 测试功率tsv的测点选择算法

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10154929

K. Hachiya

引用次数: 0

SiGe BiCMOS Technology with Embedded Microchannels based on Cu Pillar PCB Integration Enabling sub-THz Microfluidic Sensor Applications 基于铜柱PCB集成的嵌入式微通道SiGe BiCMOS技术实现亚太赫兹微流控传感器应用

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10155073

E. C. Durmaz, C. Heine, Zhibo Cao, Jens Lehmann, D. Kissinger, M. Wietstruck

引用次数: 0

Copper Electrode Surface Features and Cu-SiO2Hybrid Bonding 铜电极表面特征与cu - sio2杂化键合

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10154924

M. Murugesan, M. Sawa, E. Sone, M. Motoyoshi, M. Koyanagi, T. Fukushima

引用次数: 0

Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages 基于芯片封装的多模间互连的高效测试与诊断模式生成

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10154900

Po-Yao Chuang, Francesco Lorenzelli, S. Chakravarty, Slimane Boutobza, Cheng-Wen Wu, G. Gielen, E. Marinissen

{"title":"Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages","authors":"Po-Yao Chuang, Francesco Lorenzelli, S. Chakravarty, Slimane Boutobza, Cheng-Wen Wu, G. Gielen, E. Marinissen","doi":"10.1109/3DIC57175.2023.10154900","DOIUrl":"https://doi.org/10.1109/3DIC57175.2023.10154900","url":null,"abstract":"Chiplet-based (2.5D and 3D) multi-die packages implement large amounts of inter-die interconnects with micro-bump connections and possibly TSVs. These interconnects can be subject to manufacturing defects. The most common defects are shorts and opens, which occur both in hard and weak (= resistive) variants. Traditional interconnect automatic test pattern generation (I-ATPG) methods only cover hard defects. These methods are generally considered efficient, as their test pattern counts scale logarithmically with the number of interconnects $k$. However, they cover short defects between all interconnects, including those for which shorts are unrealistic given their relative layout positions. In this paper, we propose E2ITEST, a modified True/Complement test [1], which covers, for a given collection of interconnects, all hard and weak variants of only realistic short and open defects. Supporting fault diagnosis, E2ITEST also prevents aliasing. While it is predicted that the number of interconnects $k$ will rise significantly in the near future, E2ITEST provides a high-quality interconnect test for which the number of test patterns is constant and no longer dependent on $k$.","PeriodicalId":245299,"journal":{"name":"2023 IEEE International 3D Systems Integration Conference (3DIC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123667364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast, Accurate Assembly-Level Physical Verification of 3DIC Packages 快速，准确的装配级3DIC封装物理验证

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10155000

N. Hossam, J. Ferguson

{"title":"Fast, Accurate Assembly-Level Physical Verification of 3DIC Packages","authors":"N. Hossam, J. Ferguson","doi":"10.1109/3DIC57175.2023.10155000","DOIUrl":"https://doi.org/10.1109/3DIC57175.2023.10155000","url":null,"abstract":"Advanced packaging techniques are critical to ensuring product performance, function, and cost in the semiconductor industry. Three-dimensional integrated circuits (3DICs) offer the ultimate flexibility in product design. However, they are not without their challenges, bringing packaging technologies to the forefront for innovation. 3DICs contain multiple stacked die that achieve the required connectivity through traces on an interposer, or with special vias or bumps. Independently verifying the physical and connectivity accuracy of these discrete dies and substrates per their process rules does not ensure that the overall 2.5D/3D package assembly is correct, or will perform as expected. The Calibre 3DSTACK electronic design automation (EDA) tool provides fast, accurate, assembly-level verification of die-die or die-interposer interfaces in 3DIC designs. It operates on the interface geometries between chip designs from multiple process nodes to perform both design rule checking (DRC) alignment verification and layout vs. schematic (LVS) connectivity checking of the complete multi-die 2.5D or 3DIC system. Design engineers can also use the Calibre 3DSTACK tool to prepare the data required for coupling capacitance extraction, if required. In this paper, we explain the differences between traditional 3DIC physical verification techniques and Calibre 3DSTACK 3DIC assembly verification, and demonstrate how Calibre 3DSTACK functionality can be used to resolve many of the challenges of 3DIC physical verification while ensuring the accuracy and performance of the complete 3DIC design.","PeriodicalId":245299,"journal":{"name":"2023 IEEE International 3D Systems Integration Conference (3DIC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130195494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Review of Hybrid Integration Techniques for Integrating III-V Onta Silicon 集成III-V型Onta硅的混合集成技术综述

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10154923

Erik W. Masselink, A. Stark, Benjamin B. Yang, T. R. Harris

{"title":"Review of Hybrid Integration Techniques for Integrating III-V Onta Silicon","authors":"Erik W. Masselink, A. Stark, Benjamin B. Yang, T. R. Harris","doi":"10.1109/3DIC57175.2023.10154923","DOIUrl":"https://doi.org/10.1109/3DIC57175.2023.10154923","url":null,"abstract":"Silicon photonics promises higher on-chip communication speeds through optical interconnects, high performance LIDAR sensors, advances in biological sensors, and high performance, high-bandwidth 5G transceivers. It has the unique advantage that it is compatible with current CMOS technology. While silicon photonic devices can integrate nearly any desired photonic structure, silicon itself is an indirect bandgap semiconductor so the light source for any photonic circuit must be sourced elsewhere. Coupling a light source from off-chip remains one of the most difficult packaging, performance, and integration challenges for silicon photonics. To address these issues, myriad research efforts over the last several years have focused on heterogeneously integrating direct-bandgap materials like indium phosphide (InP) directly onto silicon photonic devices. Hybrid integration is a promising integration technique because it allows the CMOS or III-V laser diode fabrication processes to be optimized independently. This paper provides a review of state-of-the-art hybrid integration technologies, including bonding and alignment techniques, and how to integrate those with CMOS technologies. The focus will be on telecom wavelength edge coupled laser diodes since these are well established and have low coupling losses.","PeriodicalId":245299,"journal":{"name":"2023 IEEE International 3D Systems Integration Conference (3DIC)","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124479099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Welcome to 3DIC 2023 欢迎来到3DIC 2023

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3dic57175.2023.10154951

引用次数: 0