Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs

M. Naeim, Hanqi Yang, Pinhong Chen, Rong Bao, Antoine Dekeyser, G. Sisto, Moritz Brunion, Rongmei Chen, G. V. D. Plas, E. Beyne, D. Milojevic
{"title":"Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs","authors":"M. Naeim, Hanqi Yang, Pinhong Chen, Rong Bao, Antoine Dekeyser, G. Sisto, Moritz Brunion, Rongmei Chen, G. V. D. Plas, E. Beyne, D. Milojevic","doi":"10.1109/3DIC57175.2023.10155075","DOIUrl":null,"url":null,"abstract":"Multi-dies stack 3D-ICs are an extension of traditional 2-dies 3D-ICs to address the memory wall and footprint problems. This paper presents a complete Place-and-Route (PnR) flow to enable 3-dies stacked 3D-ICs from netlist partitioning to timing analysis, including original cross-dies co-optimization steps. The proposed flow is based on Integrity™ 3D-IC tool from Cadence. To demonstrate the flow, openPITON-T1 Tile design with IMEC N2 Process Design Kit (PDK) is used. The same design is implemented in normal 2D PnR flow and the proposed 3-dies stack flow. Our results show that a 3-dies stack design can achieve up to 11.4% increase in effective frequency and 50% less system footprint when compared with its 2D counterpart.","PeriodicalId":245299,"journal":{"name":"2023 IEEE International 3D Systems Integration Conference (3DIC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International 3D Systems Integration Conference (3DIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/3DIC57175.2023.10155075","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

Multi-dies stack 3D-ICs are an extension of traditional 2-dies 3D-ICs to address the memory wall and footprint problems. This paper presents a complete Place-and-Route (PnR) flow to enable 3-dies stacked 3D-ICs from netlist partitioning to timing analysis, including original cross-dies co-optimization steps. The proposed flow is based on Integrity™ 3D-IC tool from Cadence. To demonstrate the flow, openPITON-T1 Tile design with IMEC N2 Process Design Kit (PDK) is used. The same design is implemented in normal 2D PnR flow and the proposed 3-dies stack flow. Our results show that a 3-dies stack design can achieve up to 11.4% increase in effective frequency and 50% less system footprint when compared with its 2D counterpart.
使用细间距混合键合和tsv的3晶片堆叠3d - ic的设计实现
多晶片堆叠3d - ic是传统的2晶片3d - ic的延伸,以解决内存墙和占用空间问题。本文提出了一个完整的放置和路由(PnR)流程,以实现从网表划分到时序分析的3-die堆叠3d - ic,包括原始的跨die协同优化步骤。该流程基于Cadence的Integrity™3D-IC工具。为了演示流程,使用了openPITON-T1瓦片设计和IMEC N2工艺设计套件(PDK)。同样的设计在正常的二维PnR流和提出的3模堆叠流中实现。我们的研究结果表明,与2D设计相比,3 die堆叠设计可以实现有效频率提高11.4%,系统占地面积减少50%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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