2023 IEEE International 3D Systems Integration Conference (3DIC)最新文献

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Thermal Estimation for 3D-ICs Through Generative Networks 基于生成网络的3d集成电路热估计

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10154977

Priyank Kashyap, P. P. Ravichandiran, Lee Wang, D. Baron, Chau-Wai Wong, Tianfu Wu, P. Franzon

{"title":"Thermal Estimation for 3D-ICs Through Generative Networks","authors":"Priyank Kashyap, P. P. Ravichandiran, Lee Wang, D. Baron, Chau-Wai Wong, Tianfu Wu, P. Franzon","doi":"10.1109/3DIC57175.2023.10154977","DOIUrl":"https://doi.org/10.1109/3DIC57175.2023.10154977","url":null,"abstract":"Thermal limitations play a significant role in modern integrated chips (ICs) design and performance. 3D integrated chip (3DIC) makes the thermal problem even worse due to a high density of transistors and heat dissipation bottlenecks within the stack-up. These issues exacerbate the need for quick thermal solutions throughout the design flow. This paper presents a generative approach for modeling the power to heat dissipation for a 3DIC. This approach focuses on a single layer in a stack and shows that, given the power map, the model can generate the resultant heat for the bulk. It shows two approaches, one straightforward approach where the model only uses the power map and the other where it learns the additional parameters through random vectors. The first approach recovers the temperature maps with 1.2 C° or a root-mean-squared error (RMSE) of 0.31 over the images with pixel values ranging from -1 to 1. The second approach performs better, with the RMSE decreasing to 0.082 in a 0 to 1 range. For any result, the model inference takes less than 100 millisecond for any given power map. These results show that the generative approach has speed advantages over traditional solvers while enabling results with reasonable accuracy for 3DIC, opening the door for thermally aware floorplanning.","PeriodicalId":245299,"journal":{"name":"2023 IEEE International 3D Systems Integration Conference (3DIC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124959329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Thermal Cycling and Fatigue Life Analysis of a Laterally Conducting GaN-based Power Package 横向导电氮化镓基电源封装的热循环和疲劳寿命分析

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10154901

Pouria Zaghari, Sourish S. Sinha, J. Ryu, P. Franzon, D. Hopkins

{"title":"Thermal Cycling and Fatigue Life Analysis of a Laterally Conducting GaN-based Power Package","authors":"Pouria Zaghari, Sourish S. Sinha, J. Ryu, P. Franzon, D. Hopkins","doi":"10.1109/3DIC57175.2023.10154901","DOIUrl":"https://doi.org/10.1109/3DIC57175.2023.10154901","url":null,"abstract":"Thermal reliability is a critical factor in ensuring the performance and efficiency of GaN-based electronic devices. In this paper, the fatigue life assessment of a laterally conducting GaN power package that uses a two-solder hierarchy of SAC305 and Sn63/Pb37 on a 120μm thick dielectric for device attach was conducted using an FEA. The double-sided package structure also introduced thick Cu as integrated baseplate layers for mechanical mounting into higher packaging levels while providing surfaces for double-sided cooling. The internal structure varied spacer thicknesses for planarization and inclusion of package-integrated decoupling capacitors. The solder materials were simulated by using the Anand viscoplastic constitutive model. Coffin-Manson, Engelmaier, and Solomon empirical strain-based models were utilized to predict the cyclic life of the package. Based on the results, the critical solder joint location was predicted in the Sn63/Pb37 solder layer between the GaN and Cu spacer, with a strain range of 0.02797. The worst-case life prediction for the module was 150 cycles using the Coffin-Manson model.","PeriodicalId":245299,"journal":{"name":"2023 IEEE International 3D Systems Integration Conference (3DIC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128151683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Chiplet Set For Artificial Intelligence 人工智能芯片套装

2023 IEEE International 3D Systems Integration Conference (3DIC) Pub Date : 2023-05-10 DOI: 10.1109/3DIC57175.2023.10154953

Joshua A. Stevens, Tse-Han Pan, P. P. Ravichandiran, P. Franzon

{"title":"Chiplet Set For Artificial Intelligence","authors":"Joshua A. Stevens, Tse-Han Pan, P. P. Ravichandiran, P. Franzon","doi":"10.1109/3DIC57175.2023.10154953","DOIUrl":"https://doi.org/10.1109/3DIC57175.2023.10154953","url":null,"abstract":"The design reuse strategy has significantly shortened the time required to create complex System on Chips (SoCs). However, when introducing new intellectual properties (IPs), the monolithic SoC methodology requires a re-run of system-level validation steps, incurring significant costs. Partitioning the design into chiplets over an interposer would mitigate these issues by consigning the IP updates to the individual chiplet. This paper presents a chipletized design used for Artificial Intelligence (AI). This design details a scalable AI chiplet set, along with Central Processing Units (CPUs). The AI chiplet set includes an Long Short Term Memory (LSTM) Application Specific Instruction Set Processor (ASIP) for accelerating inference and training and an Sparse Convolution Neural Network (SCNN) ASIP for accelerating inference through a zero-skipping technique. The CPUs control AI accelerators and handle general tasks. The accelerators and CPUs have an AXI crossbar Network on Chip (NoC) for memory and one for controlling the accelerators. This project has two phases: phase one, IP validation with an emulated interposer (No interposer, connect chiplets through back end of line (BEOL) metal layers), and phase two, connecting validated IP through an interposer. This paper focuses on phase one, which uses the United Semiconductor Japan Co. (USJC) 55 nm LP process to fabricate the design. The chiplets' clock frequencies range from 200 - 400 MHz.","PeriodicalId":245299,"journal":{"name":"2023 IEEE International 3D Systems Integration Conference (3DIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127754612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

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